Differential source follower with current steering devices

1. An apparatus comprising:

a differential source follower coupled to a first input and a second input, wherein the first input is separate from the second input;

first and second current steering devices coupled to the differential source follower;

a current source coupled to the first and second current steering devices; and

a first capacitor coupled to the first current steering device and the differential source follower,

wherein the differential source follower comprises:

a source follower comprising:

a p-type device coupled in series with the first current steering device, and also coupled to the first input;

a first n-type device coupled in series with the p-type device, wherein the first n-type device is biased by a bias, wherein drain terminals of the p-type and the first n-type devices are coupled to the first capacitor; and

a second n-type transistor having a gate terminal coupled to the first capacitor and a drain terminal coupled to a first output.

2. The apparatus of claim 1 , comprising:

a second capacitor coupled to the second current steering device and the differential source follower.

3. The apparatus of claim 2 comprising a bias generator to generate the bias for the differential source follower.

4. The apparatus of claim 3 comprising:

a third capacitor coupled to the first input and the second current steering device; and

a fourth capacitor coupled to second input and the second current steering device, wherein the fourth capacitor is coupled to a first output, and wherein the third capacitor is coupled to a second output.

5. The apparatus of claim 1 , wherein the differential source follower comprises a differential class AB source follower.

6. The apparatus of claim 1 , wherein the current source is a p-type current source, and wherein the apparatus comprises a fifth capacitor coupled to a gate terminal and a source terminal of the current source.

7. The apparatus of claim 3 , wherein the source follower is a first source follower, wherein the differential source follower comprises a second source follower which includes:

a p-type device coupled in series with the second current steering device, and also coupled to the second input; and

an n-type device coupled in series with the p-type device of the second source follower, wherein the n-type device of the second source follower is biased by the bias from the bias generator, and wherein drain terminals of the p-type and the n-type devices of the second source follower are coupled to the second capacitor.

8. The apparatus of claim 7 , wherein the n-type transistor of the second source follower is a first n-type transistor, wherein the second source follower comprises a second n-type transistor having a gate terminal coupled to the second capacitor and a drain terminal coupled to the second output.

9. The apparatus of claim 2 , wherein a gate terminal of the first current steering device is coupled to a first resistor, which is coupled to the bias.

10. The apparatus of claim 9 , wherein a gate terminal of the second current steering device is coupled to a second resistor, which is coupled to the bias.

11. An apparatus comprising:

a differential analog front-end;

a differential track and hold circuitry coupled to an output of the differential analog front-end; and

a buffer coupled to an output of the differential track and hold circuitry, wherein the buffer comprises:

a differential source follower coupled to a first input and a second input, wherein the first input is separate from the second input, wherein the first and second inputs are first and second outputs of the differential track and hold circuitry, respectively;

first and second current steering devices coupled to the differential source follower;

a current source coupled to the first and second current steering devices; and

a first capacitor coupled to the first current steering device and the differential source follower, wherein the differential source follower comprises:

a source follower comprising:

a p-type device coupled in series with the first current steering device, and also coupled to the first input;

a first n-type device coupled in series with the p-type device, wherein the first n-type device is biased by a bias, wherein drain terminals of the p-type and the first n-type devices are coupled to the first capacitor; and

a second n-type device having a gate terminal coupled to the first capacitor and a drain terminal coupled to the first output.

12. The apparatus of claim 11 , wherein the differential track and hold circuitry is a first differential track and hold circuitry, and wherein the apparatus comprises a second differential track and hold circuitry coupled to first and second output of the differential source follower.

13. The apparatus of claim 12 comprising an analog-to-digital converter (ADC) coupled to the second differential track and hold circuitry.

14. The apparatus of claim 13 comprising a feed-forward equalizer coupled to an output of the ADC.

15. The apparatus of claim 14 comprising a decision feedback equalizer coupled to an output of the feed-forward equalizer.

16. The apparatus of claim 15 comprising a clock data recovery (CDR) circuitry coupled to the feed-forward equalizer and the decision feedback equalizer.

17. The apparatus of claim 11 , comprising:

a second capacitor coupled to the second current steering device and the differential source follower; and

a bias generator to generate the bias for the differential source follower.

18. A system comprising:

a memory;

a processor coupled to the memory, wherein the processor includes a buffer which includes:

a differential source follower coupled to a first input and a second input, wherein the first input is separate from the second input;

first and second current steering devices coupled to the differential source follower;

a current source coupled to the first and second current steering devices; and

a first capacitor coupled to the first current steering device and the differential source follower, wherein the differential source follower comprises:

a source follower comprising:

a p-type device coupled in series with the first current steering device, and also coupled to the first input;

a first n-type device coupled in series with the p-type device, wherein the first n-type device is biased by a bias, wherein drain terminals of the p-type and the first n-type devices are coupled to the first capacitor; and

a second n-type device having a gate terminal coupled to the first capacitor and a drain terminal coupled to a first output; and

a wireless interface to allow the processor to communicate with another device.

19. The system of claim 18 , wherein the buffer comprises:

a second capacitor coupled to the second current steering device and the differential source follower;

a third capacitor coupled to the first input and the second current steering device; and

a fourth capacitor coupled to second input and the second current steering device, wherein the fourth capacitor is coupled to a first output, and wherein the third capacitor is coupled to a second output.