Switch with data and control path systolic array
The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
1. A method for switching, comprising:
receiving a transaction layer packet (TLP) at an uplink port of a switch;
at the switch:
determining a nature of the TLP by evaluating a parameter of the TLP at a filter coupled to the uplink port;
determining if the TLP should be routed to a systolic array at the switch based on the nature of the TLP determined by the filter;
routing the TLP to the systolic array at the switch based on a determination that the TLP should be routed to the systolic array at the switch;
analyzing, at the switch, the TLP in the systolic array; and
forwarding the TLP to a destination port of the switch based on the analysis of the TLP performed by the systolic array of the switch.
2. The method of claim 1 , wherein only a header portion of the TLP is routed to the systolic array.
3. The method of claim 1 , wherein the TLP routed to the systolic array is the received TLP.
4. The method of claim 1 , wherein the TLP routed to the systolic array is a replica of the received TLP.
5. The method of claim 1 , wherein the systolic array has an interface to communicate with a plurality of destination ports.
6. The method of claim 5 , wherein each of the destination ports has an associated filter.
7. A switch, comprising:
an uplink port for receiving a transaction layer packet (TLP) at the switch;
a filter coupled to the uplink port, the filter for determining a nature of the TLP received at the uplink port by evaluating a parameter of the received TLP, determining if the TLP should be routed to a systolic array at the switch based on the nature of the TLP determined by the filter and routing the TLP to the systolic array at the switch based on a determination that the TLP should be routed to the systolic array at the switch;
the systolic array for analyzing the TLP at the switch and forwarding the TLP to a destination port of the switch based on the analysis of the TLP performed by the systolic array of the switch; and
a destination port for receiving the TLP.
8. The switch of claim 7 , wherein the systolic array only receives a header portion of the TLP.
9. The switch of claim 7 , wherein the systolic array receives the TLP as it was received by the uplink port.
10. The switch of claim 7 , wherein the filter creates a replica of the TLP and forwards the replica to the systolic array.
11. The switch of claim 7 , wherein the destination port comprises a plurality of downlink ports.
12. The switch of claim 7 , wherein the systolic array comprises an interface to communicate with a plurality of downlink ports.
13. The switch of claim 12 , wherein each of the downlink ports has an associated filter.
14. The switch of claim 7 , wherein the systolic array comprises a plurality of data processing units (DPUs).