Semiconductor device and display device including the same
A semiconductor device with reduced power consumption and a display device including the semiconductor are provided. The semiconductor device generates a bias voltage that is to be supplied to a buffer amplifier. When the display device displays a still image, a data signal for updating the image need not be supplied from the buffer amplifier to a pixel array in the next frame; therefore, the circuit is configured so that the buffer amplifier is brought into a standby state (temporarily stopped). Specifically, input of a reference current from a BGR circuit to the semiconductor is stopped and a bias voltage is applied from the semiconductor device to the buffer amplifier to temporarily stop the operation of the buffer amplifier.
1. A semiconductor device comprising:
a first circuit comprising a first transistor;
a second circuit comprising a second transistor and a third transistor;
a third circuit comprising a fourth transistor;
a fourth circuit comprising a fifth transistor; and
a fifth circuit comprising a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor and one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the first transistor is directly connected to a gate of the first transistor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein a gate of the second transistor is electrically connected to a first output terminal,
wherein the gate of the second transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to a second output terminal,
wherein the second transistor is a p-channel transistor, and
wherein the third transistor is an n-channel transistor.
2. The semiconductor device according to claim 1 , wherein the other of the source and the drain of each of the first transistor, the third transistor, the fourth transistor, and the sixth transistor is electrically connected to a wiring for supplying a low-level potential.
3. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the fifth transistor are electrically connected to a wiring for supplying a high-level potential.
4. The semiconductor device according to claim 1 ,
wherein the gate of the fourth transistor and the gate of the sixth transistor are electrically connected to a wiring for supplying a standby signal, and
wherein a gate of the fifth transistor is electrically connected to a wiring for supplying for an inversion signal of the standby signal.
5. The semiconductor device according to claim 1 , wherein each of a channel formation region of the first transistor, the third transistor, the fourth transistor, and the sixth transistor comprises an oxide semiconductor.
6. The semiconductor device according to claim 1 , wherein each of the fourth transistor and the sixth transistor comprises a back gate.
7. A semiconductor device comprising:
a first circuit comprising a first transistor;
a second circuit comprising a second transistor and a third transistor;
a third circuit comprising a fourth transistor;
a fourth circuit comprising a fifth transistor;
and a fifth circuit comprising a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the third transistor and one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the first transistor is directly connected to a gate of the first transistor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein a gate of the second transistor is electrically connected to a first output terminal, wherein the gate of the second transistor is directly connected to one of a source and a drain of the fifth transistor,
wherein a gate of the fourth transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to a second output terminal,
wherein when the semiconductor device is in a driving state, the second circuit is configured to output a first bias voltage from the first output terminal and a second bias voltage from the second output terminal, and
wherein when the semiconductor device is in a standby state, the third circuit is configured to apply a first low-level potential to the first circuit and the second circuit, the fourth circuit is configured to output a high-level potential to the first output terminal, and the fifth circuit is configured to output a second low-level potential to the second output terminal.
8. The semiconductor device according to claim 7 ,
wherein the second transistor is a p-channel transistor, and
wherein the third transistor is an n-channel transistor.
9. The semiconductor device according to claim 7 , wherein the other of the source and the drain of each of the first transistor, the third transistor, the fourth transistor, and the sixth transistor is electrically connected to a wiring for supplying a low-level potential.
10. The semiconductor device according to claim 7 , wherein the other of the source and the drain of the second transistor and the other of the source and the drain of the fifth transistor are electrically connected to a wiring for supplying a high-level potential.
11. The semiconductor device according to claim 7 ,
wherein the gate of the fourth transistor and the gate of the sixth transistor are electrically connected to a wiring for supplying a standby signal, and
wherein a gate of the fifth transistor is electrically connected to a wiring for supplying for an inversion signal of the standby signal.
12. The semiconductor device according to claim 7 , wherein each of a channel formation region of the first transistor, the third transistor, the fourth transistor, and the sixth transistor comprises an oxide semiconductor.
13. The semiconductor device according to claim 7 , wherein each of the fourth transistor and the sixth transistor comprises a back gate.