Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length.
1. A method of manufacturing a semiconductor device, comprising:
forming a WELL region in a substrate;
implanting conductive-type dopants in the WELL region to form a first drift region and a second drift region;
forming a gate on the WELL region, the first drift region and the second drift region;
forming a sidewall spacer adjacent to the gate; and
forming a source region to extend from a boundary of the sidewall spacer,
wherein a mask for forming the first drift region and the second drift region surrounds a mask for forming an active region, and the source region and a drain region are formed in the active region.
2. The method of claim 1 , wherein the forming the gate on the WELL region further comprises forming the gate to overlap the first drift region or the second drift region by an overlapping length that is 5% to 25% of a length of the gate.
3. The method of claim 1 , wherein the spacer does not overlap a virtual center line of the gate.
4. The method of claim 1 , wherein, in a top view of the substrate, the mask for forming the first drift region and the second drift region has a first portion spaced apart from a second portion, and the first and second drift regions are formed in the first and second portions, respectively.
5. The method of claim 4 , wherein, in the top view of the substrate, each of the first portion and the second portion partially overlaps a mask for forming the gate.
6. The method of claim 1 , further comprising forming a first trench isolation and a second isolation in the substrate, wherein each of the first trench isolation and the second isolation has a depth deeper than a depth of the first drift region and a depth of the second drift region.
7. The method of claim 1 , wherein the mask for forming the first drift region and the second drift region extends over a device isolation layer, such that the mask overlaps the device isolation layer.
8. A method of manufacturing a semiconductor device, comprising:
forming a WELL region in a substrate;
implanting conductive-type dopants in the WELL region to form a first drift region and a second drift region;
forming a gate on the WELL region, the first drift region and the second drift region;
forming a sidewall spacer adjacent to the gate; and
forming a source region to extend from a boundary of the sidewall spacer, wherein, in a top view of the substrate, a mask for forming the first drift region and the second drift region has a maximum vertical length greater than a maximum vertical length of a mask for forming the gate.
9. A method of manufacturing a semiconductor device, comprising:
forming a WELL region in a substrate;
implanting conductive-type dopants in the WELL region to form a drift region;
forming a gate on the WELL region;
forming a sidewall spacer adjacent to the gate; and
forming a first region in the WELL region to extend from a boundary of the sidewall spacer;
wherein the drift region partially encloses the first region, completely overlaps an entire length of the sidewall spacer, and partially overlaps a length of the gate,
wherein a mask for forming the drift region surrounds a mask for forming an active region, and the first region is formed in the active region.
10. The method of claim 9 , wherein the spacer does not overlap a virtual center line of the gate.
11. The method of claim 9 , wherein, in a top view of the substrate, the mask for forming the drift region has a maximum vertical length greater than a maximum vertical length of a mask for forming the gate.
12. The method of claim 9 , wherein, in a top view of the substrate, the mask for forming the drift region has a first portion spaced apart from a second portion.
13. The method of claim 12 , wherein, in the top view of the substrate, each of the first portion and the second portion partially overlaps a mask for forming the gate.
14. The method of claim 9 , further comprising forming a first trench isolation and a second isolation in the substrate, wherein each of the first trench isolation and the second isolation has a depth deeper than a depth of the drift region.
15. The method of claim 9 , wherein, in a top view of the substrate, the mask for forming the drift region extends over a device isolation layer, such that the mask overlaps the device isolation layer.
16. The method of claim 9 , wherein, in a top view of the substrate, the mask for forming the drift region has a lateral length greater than a length between device isolation layers.
17. The method of claim 9 , wherein the first region is a drain region or a source region.