IP Library Granted Patent US 10,593,567
Granted Patent B2
US 10,593,567 · App. 16/301,448 · Granted Mar 17, 2020

Integrated circuit package and method of manufacturing the same

Inventors: Ignatius Josephus van Dommelen (Vorstenbosch, NL); Johannes Stephanus Jansen (Wijchen, NL)
Assignee: Sencio B.V.
H01L21/565B29C45/14B29C45/14639H01L21/561H01L23/31H01L23/3157H01L23/4951H01L23/4952H01L23/49531H01L23/49541H01L24/00H01L24/48H01L23/3107H01L2224/45099H01L2224/48091H01L2224/48105H01L2224/48106H01L2224/48177H01L2224/48247H01L2224/49175H01L2224/97
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Quick Facts
Patent No.
US 10,593,567
App. No.
16/301,448
Granted
Mar 17, 2020
Kind
B2
Abstract

Method of making an integrated circuit package, by a) providing a plurality of die members ( 4 a, 4 b ) connected to respective electrical contact members ( 8 a, 8 b ) in a mould; b) providing a mould insert in contact with at least a part of a first upper surface ( 6 a ) of a first die member ( 4 a ); c) encasing the plurality of die members ( 4 a, 4 b ) and the respective electrical contact members ( 8 a, 8 b ) into a package collection body ( 3 ); and d) cutting the package collection body ( 3 ) into at least two separate integrated circuit packages ( 3 a, 3 b ) along a first cutting line (S 1 ) extending through the package collection body ( 3 ) and separating the plurality of die members ( 4 a, 4 b ). The mould insert as provided in step b) extends across a part of the first cutting line (S 1 ).

Claims (17)

1. A method of making an integrated circuit package, comprising the steps of

a) providing a plurality of die members connected to respective electrical contact members in a mould;

b) providing a mould insert in contact with at least a part of a first upper surface of a first die member;

c) encasing the plurality of die members and the respective electrical contact members into a package collection body; and

d) cutting the package collection body into at least two separate integrated circuit packages along a first cutting line extending through the package collection body and separating the plurality of die members, wherein the mould insert as provided in step b) extends across a part of the first cutting line, thereby forming a side opening in a side surface of each of the at lease two separate integrated circuit packages.

2. The method according to claim 1 , further comprising providing a second die member mirrored with respect to the first die member along the first cutting line.

3. The method according to claim 1 , wherein the at least two separate integrated circuit packages Quad Flat No-Lead (QFN) packages, Land Grid Array (LGA) or Ball Grid Array (BGA) packages.

4. The method according to claim 1 , further comprising arranging the plurality of die members and respective electrical contact members in an array.

5. The method according to claim 1 , wherein the first die member comprises an active element, such as a combustion starting element or a sensor element.

6. The method according to claim 1 , wherein the respective electrical contact members are not mirrored with respect to the first cutting line.

7. The method according to claim 1 , wherein the respective electrical contact members are mirrored with respect to the first cutting line.

8. The method according to claim 1 , further comprising arranging the mould insert symmetrically over the first cutting line.

9. The method according to claim 1 , further comprising selecting a circular, elliptical, square, rectangular or polygonal shape for the mould insert.

10. An integrated circuit package, comprising a die member connected to one or more electrical contact members encased in a package, and wherein a die opening is provided exposing at least a part of the die member, wherein one side surface of the package is a straight surface,

wherein the die opening comprises an upper opening extending from an upper surface of the package to an upper surface of the die member, and a side opening within the straight surface and extending from the straight surface to the upper surface of the die member wherein the side opening is formed as a cross section of the upper opening.

11. The integrated circuit package according to claim 10 , wherein the upper opening has a border wall extending from the upper major surface to the upper surface of the die member.

12. The integrated circuit package according to claim 10 , wherein the die member comprises a combustion starting element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2024
From: SENCIO B.V.
To: NEWAYS ADVANCED MICROSYSTEMS B.V.
Reel/Frame 068078/0055 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2018
From: VAN DOMMELEN, IGNATIUS JOSEPHUS; JANSEN, JOHANNES STEPHANUS
To: SENCIO B.V.
Reel/Frame 047750/0751 →
Priority Claims (1)
EP 16170345 · May 19, 2016 · regional
Continuity (1)
Related Publication 20190295860A1 · Sep 26, 2019