IP Library Granted Patent US 10,575,402
Granted Patent B2
US 10,575,402 · App. 16/336,135 · Granted Feb 25, 2020

Resin composition, wiring layer laminate for semiconductor, and semiconductor device

Inventors: Shinichiro Abe (Tokyo, JP); Kazuhiko Kurafuchi (Tokyo, JP); Tomonori Minegishi (Tokyo, JP); Kazuyuki Mitsukura (Tokyo, JP); Masaya Toba (Tokyo, JP)
Assignee: HITACHI CHEMICAL COMPANY, LTD.
H05K1/0373C08L79/08H01L23/49811H01L23/49822H01L23/5383H05K3/4655C08K3/013C08L2203/202
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Quick Facts
Patent No.
US 10,575,402
App. No.
16/336,135
Granted
Feb 25, 2020
Kind
B2
Abstract

One aspect of the present invention relates to a resin composition comprising a curable resin and a curing agent, which is used for forming an inter-wiring layer insulating layer in contact with a copper wiring.

Claims (31)

1. A wiring layer laminate for a semiconductor, comprising:

a plurality of wiring layers comprising

an organic insulating layer,

a copper wiring disposed in the organic insulating layer, and

a barrier metal film separating the copper wiring and the organic insulating layer; and

an inter-wiring layer insulating layer disposed between the plurality of wiring layers;

wherein a portion of a surface of the copper wiring is exposed to a principal surface side of one or both of the wiring layer,

the exposed surface of the copper wiring is in contact with the inter-wiring layer insulating layer, and

the inter-wiring layer insulating layer is a layer having a moisture absorptivity of 1% by mass or less after placed in an environment at 130° C. and a relative humidity of 85% for 200 hours.

2. The wiring layer laminate for a semiconductor according to claim 1 , wherein the inter-wiring layer insulating layer is a cured product of a resin composition comprising:

a curable resin; and

a curing agent.

3. The wiring layer laminate for a semiconductor according to claim 2 , wherein the curable resin has at least two maleimide groups and a divalent hydrocarbon group.

4. The wiring layer laminate for a semiconductor according to claim 3 , wherein the hydrocarbon group comprises a chain alkylene group having a main chain with 4 or more carbon atoms.

5. The wiring layer laminate for a semiconductor according to claim 3 , wherein the hydrocarbon group has 8 or more carbon atoms.

6. The wiring layer laminate for a semiconductor according to claim 3 , the hydrocarbon group is a group represented by the following formula (II):

wherein R 2 and R 3 each independently represent an alkylene group, and R 4 and R 5 each independently represent an alkyl group.

7. The wiring layer laminate for a semiconductor according to claim 3 , the curing agent comprises a radical photopolymerization initiator.

8. The wiring layer laminate for a semiconductor according to claim 3 , wherein the resin composition further comprises a compound haying a (meth)acryloyl group.

9. The wiring layer laminate for a semiconductor according to claim 3 , wherein the resin composition further comprises a coupling agent.

10. The wiring layer laminate for a semiconductor according to claim 2 , the curable resin has a divalent organic group having at least 2 imide bonds.

11. The wiring layer laminate for a semiconductor according to claim 10 , the divalent organic group is a group represented by the following formula (I):

wherein R 1 represents a tetravalent organic group.

12. The wiring layer laminate for a semiconductor according to claim 2 , wherein the resin composition further comprises a thermoplastic resin.

13. The wiring layer laminate for a semiconductor according to claim 1 , wherein the organic insulating layer is a layer formed from photosensitive insulating resin.

14. The wiring layer laminate for a semiconductor according to claim 1 , wherein a dielectric constant of the inter-wiring layer insulating layer upon application of 10 GHz is 3.0 or less.

15. The wiring layer laminate for a semiconductor according to claim 1 , wherein a dielectric loss tangent of the inter-wiring layer insulating layer upon application of 10 GHz is 0.005 or less.

16. The wiring layer laminate for a semiconductor according to claim 1 , wherein a 5% weight loss temperature of the inter-wiring layer insulating layer is 300° C. or more.

17. A semiconductor device comprising:

the wiring laminate for a semiconductor according to claim 1 ; and

a semiconductor element electrically connected to the copper wiring.

Assignments (4)
CHANGE OF ADDRESS Recorded Feb 14, 2024
From: RESONAC CORPORATION
To: RESONAC CORPORATION
Reel/Frame 066599/0037 →
CHANGE OF NAME Recorded Mar 3, 2023
From: SHOWA DENKO MATERIALS CO., LTD.
To: RESONAC CORPORATION
Reel/Frame 062946/0125 →
CHANGE OF NAME Recorded Mar 2, 2023
From: HITACHI CHEMICAL COMPANY, LTD.
To: SHOWA DENKO MATERIALS CO., LTD.
Reel/Frame 062917/0865 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: ABE, SHINICHIRO; KURAFUCHI, KAZUHIKO; MINEGISHI, TOMONORI; MITSUKURA, KAZUYUKI; TOBA, MASAYA
To: HITACHI CHEMICAL COMPANY, LTD.
Reel/Frame 049654/0012 →
Cited By (1)
US 12,655,254