3D semiconductor device and structure

1. A method to construct a 3D system, the method comprising:

providing a base wafer; and then

transferring a first memory wafer on top of said base wafer; and then

thinning said first memory wafer; and then

transferring a second memory wafer on top of said first memory wafer; and then

thinning said second memory wafer; and

transferring a memory control on top of said second memory wafer; and then

thinning said memory control,

wherein said first memory wafer comprises a cut-layer, and

wherein said thinning of said first memory wafer comprises using said cut-layer to control the thickness of said first memory wafer.

2. The method according to claim 1 ,

wherein said thickness of said first memory wafer is less than 4 microns.

3. The method according to claim 1 , further comprising:

forming a logic stratum; and

forming a thermal isolation layer disposed between said logic stratum and said second memory wafer,

wherein said first memory wafer comprises a first memory and said second memory wafer comprises a second memory, and

wherein said thermal isolation layer is designed so during said 3D system operation a first temperature of said first memory or said second memory is at least 20° C. lower than a second temperature of said logic stratum.

4. The method according to claim 1 , further comprising:

thinning at least one of said first memory wafer, or said second memory wafer, or said memory control to a thickness of less than 100 nm.

5. The method according to claim 1 ,

wherein said first memory wafer comprises a first memory and said second memory wafer comprises a second memory, and

wherein said first memory or said second memory comprises one of the following:

i. DRAM, or

ii. SRAM, or

iii. Floating Body type memory, or

iv. STT-RAM, or

v. R-RAM, or

vi. M-RAM, or

vii. T-RAM.

6. The method according to claim 1 , further comprising:

performing a step of memory test,

wherein said first memory wafer comprises a first memory and said second memory wafer comprises a second memory; and then

performing a step using a first portion of said first memory as an alternative for a portion of said second memory or a portion of said second memory as an alternative for a second portion of said first memory.

7. The method according to claim 1 ,

wherein said 3D system has a planar die size greater than 40×40 mm 2 .

8. A 3D device, the device comprising:

a first stratum comprising a first bit-cell array, said first bit-cell array comprises a hundred independent first rows;

a second stratum comprising a second bit-cell array, said second bit-cell array comprises a hundred independent second rows,

wherein said second stratum overlays said first stratum; and

at least one hundred vertical bit-lines each connected to a respective one hundred horizontal first bit-lines and one hundred horizontal second bit-lines,

wherein said hundred horizontal first bit-lines provide access for control of said first bit-cell array,

wherein said hundred horizontal second bit-lines provide access for control of said second bit-cell array, and

wherein each of said hundred vertical bit-lines could be used to provide access for control of a different one of said hundred independent first rows, or control of a different one of said hundred independent second rows.

9. The 3D device according to claim 8 ,

wherein said hundred horizontal first bit-lines are spaced apart from each other by less than 200 nm.

10. The device according to claim 8 , further comprising:

a logic stratum; and

a thermal isolation layer disposed between said logic stratum and said first stratum,

wherein said thermal isolation layer is designed so during said device operation a first temperature of said first stratum is at least 20° C. lower than a second temperature of said logic stratum.

11. The device according to claim 8 , further comprising:

at least one additional stratum,

wherein said at least one additional stratum has a thickness of less than 100 nm, and

wherein said at least one additional stratum comprises a plurality of transistors and at least one interconnecting metal layer.

12. The device according to claim 8 ,

wherein said first bit-cell array or said second bit-cell array comprises one of the following:

i. DRAM, or

ii. SRAM, or

iii. Floating Body type memory, or

iv. STT-RAM, or

v. R-RAM, or

vi. M-RAM, or

vii. T-RAM.

13. The device according to claim 8 , further comprising:

a third stratum,

wherein said first stratum comprises a first word-line controlling at least one of said first bit-cell arrays,

wherein said second stratum comprises a second word-line, overlaying said first word-line, controlling at least one of said second bit-cell arrays, and

wherein said third stratum comprises a control circuit to enable use of said second word-line as an alternative to said first word-line or use of said first word-line as an alternative to said second word-line.

14. The device according to claim 8 ,

wherein at least one of said first stratum and said second stratum comprises a single crystal region,

wherein a single crystal transistor is built in said single crystal region and interconnected by metal layers, and

wherein said single crystal region has a planar size greater than 40×40 mm 2 .

15. A 3D device, the device comprising:

a first stratum of first bit-cell memory arrays;

a second stratum of second bit-cell memory arrays;

a third stratum,

wherein said second stratum overlays said first stratum,

wherein said third stratum overlays said second stratum,

wherein said third stratum comprises a plurality of word-line decoders to control said first bit-cell memory arrays and said second bit-cell memory arrays;

a logic stratum overlaying said third stratum; and

a thermal isolation layer disposed between said logic stratum and said second stratum,

wherein said thermal isolation layer is designed so during operation of said device a first temperature of said first stratum is at least 20° C. lower than a second temperature of said logic stratum.

16. The device according to claim 15 ,

wherein at least one of said first stratum, said second stratum, and logic stratum comprises a single crystal region,

wherein a single crystal transistor is built in said single crystal region and interconnected by metal layers, and

wherein said single crystal region has a planar size greater than 40×40 mm 2 .