Semiconductor memory devices
Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.
1 . A semiconductor memory device comprising:
a cell array structure including a memory cell array and a plurality of first bonding pads electrically connected to the memory cell array; and
a peripheral circuit structure including a plurality of second bonding pads bonded to the plurality of first bonding pads, respectively,
wherein the cell array structure includes:
a lower dielectric layer including a first surface and a second surface opposite to the first surface;
a stack structure including a plurality of horizontal electrodes that are stacked in a vertical direction on the first surface of the lower dielectric layer;
a vertical structure including a plurality of vertical conductive patterns that extend in the vertical direction and cross the plurality of horizontal electrodes; and
an input/output pad on the second surface of the lower dielectric layer.
2 . The semiconductor memory device of claim 1 ,
wherein the cell array structure includes a bit-line connection region and a word-line connection region,
wherein the plurality of first bonding pads include:
a plurality of first upper bonding pads electrically connected to the plurality of vertical conductive patterns, respectively, on the bit-line connection region; and
a plurality of second upper bonding pads electrically connected to the plurality of horizontal electrodes, respectively, on the word-line connection region.
3 . The semiconductor memory device of claim 2 , wherein
the cell array structure further includes a plurality of power capacitors and an input/output plug on a first peripheral region, and
the plurality of first bonding pads further include a plurality of third upper bonding pads, and each of the plurality of third upper bonding pads is electrically connected to a respective one of the plurality of power capacitors and the input/output plug on the first peripheral region.
4 . The semiconductor memory device of claim 3 , wherein, on the first peripheral region, the input/output pad is electrically connected to the input/output plug.
5 . The semiconductor memory device of claim 2 , further comprising a plurality of dummy pads on the bit-line connection region and the word-line connection region, the plurality of dummy pads being on the second surface of the lower dielectric layer.
6 . The semiconductor memory device of claim 5 , further comprising a passivation layer on the second surface of the lower dielectric layer,
wherein the passivation layer extends on top surfaces of the plurality of dummy pads and includes an opening that exposes a top surface of the input/output pad.
7 . The semiconductor memory device of claim 2 ,
wherein the peripheral circuit structure includes:
a first core region that overlaps the bit-line connection region and includes a plurality of sense amplifiers; and
a second core region that overlaps the word-line connection region and includes a plurality of sub-word line drivers.
8 . The semiconductor memory device of claim 7 , wherein the plurality of second bonding pads include:
a plurality of first lower bonding pads on the first core region and electrically connected to the plurality of sense amplifiers, respectively; and
a plurality of second lower bonding pads on the second core region and electrically connected to the plurality of sub-word line drivers, respectively,
wherein the plurality of first lower bonding pads are bonded to the plurality of first upper bonding pads, respectively, and
wherein the plurality of second lower bonding pads are bonded to the plurality of second upper bonding pads, respectively.
9 . The semiconductor memory device of claim 1 , wherein
the plurality of horizontal electrodes of the stack structure include, respectively, a plurality of word lines extending parallel to the first surface of the lower dielectric layer, and
the plurality of vertical conductive patterns of the vertical structure include, respectively, a plurality of bit lines that extend perpendicular to the first surface of the lower dielectric layer.
10 . The semiconductor memory device of claim 9 , wherein the cell array structure further includes:
a plurality of semiconductor patterns that cross the plurality of word lines and are stacked in the vertical direction that is perpendicular to the first surface of the lower dielectric layer; and
a plurality of data storage elements in contact with first lateral surfaces of the plurality of semiconductor patterns, respectively.
11 . The semiconductor memory device of claim 10 , wherein each of the plurality of bit lines is in contact with second lateral surfaces of the plurality of semiconductor patterns, the second lateral surfaces being opposite to the first lateral surfaces.
12 . A semiconductor memory device, comprising:
a cell array structure including a plurality of memory cells and a plurality of first bonding pads electrically connected to the plurality of memory cells, respectively, the cell array structure including a cell array region on which the plurality of memory cells are provided and a first peripheral region adjacent the cell array region;
a peripheral circuit structure including a plurality of peripheral circuits and a plurality of second bonding pads electrically connected to the plurality of peripheral circuits, respectively, the plurality of second bonding pads being bonded to the plurality of first bonding pads, respectively; and
a passivation layer including a plurality of input/output pads and a plurality of dummy pads,
wherein, when viewed in cross section, the cell array structure is between the passivation layer and the peripheral circuit structure,
wherein the plurality of input/output pads overlap the first peripheral region of the cell array structure, and
wherein the plurality of dummy pads overlap the cell array region of the cell array structure.
13 . The semiconductor memory device of claim 12 , wherein the cell array structure further includes a plurality of power capacitors and an input/output plug on the first peripheral region,
wherein each of the plurality of first bonding pads is electrically connected to a respective one of the plurality of power capacitors and the input/output plug on the first peripheral region.
14 . The semiconductor memory device of claim 12 , wherein the cell array structure further includes:
a stack structure including a plurality of word lines and a plurality of interlayer dielectric patterns that are alternately stacked;
a plurality of semiconductor patterns that are stacked and cross the plurality of word lines;
a bit line that crosses the plurality of word lines and contacts first lateral surfaces of the plurality of semiconductor patterns; and
a plurality of data storage elements contacting second lateral surfaces of the plurality of semiconductor patterns, respectively.
15 . The semiconductor memory device of claim 14 ,
wherein the cell array region of the cell array structure includes a bit-line connection region and a word-line connection region,
wherein the plurality of first bonding pads include:
a plurality of first upper bonding pads electrically connected to a plurality of bit lines, respectively, on the bit-line connection region; and
a plurality of second upper bonding pads electrically connected to the plurality of word lines, respectively, on the word-line connection region.
16 . The semiconductor memory device of claim 15 ,
wherein the peripheral circuit structure includes:
a first core region that overlaps the bit-line connection region and includes a plurality of sense amplifiers; and
a second core region that overlaps the word-line connection region and includes a plurality of sub-word line drivers.
17 . The semiconductor memory device of claim 12 , wherein the peripheral circuit structure includes:
a core region that overlaps the cell array region and includes a plurality of sense amplifiers and a plurality of sub-word line drivers; and
a second peripheral region that overlaps the first peripheral region.
18 . A semiconductor memory device, comprising:
a cell array structure including a plurality of first bonding pads electrically connected to a plurality of memory cells, respectively, the cell array structure including a cell array region on which the plurality of memory cells are provided and a first peripheral region adjacent the cell array region, the cell array region including a bit-line connection region and a word-line connection region; and
a peripheral circuit structure including a plurality of peripheral circuits and a plurality of second bonding pads that are electrically connected to the plurality of peripheral circuits, respectively, and are bonded to the plurality of first bonding pads, respectively,
wherein the cell array structure includes:
a lower dielectric layer including a first surface and a second surface that are opposite to each other;
a stack structure including a plurality of word lines that are stacked in a direction perpendicular to the first surface of the lower dielectric layer;
a vertical structure including a plurality of bit lines in the stack structure;
an input/output plug in a dielectric layer on the stack structure;
an input/output pad on the second surface of the lower dielectric layer on the first peripheral region, the input/output pad being electrically connected to the input/output plug; and
a plurality of dummy pads on the second surface of the lower dielectric layer on the bit-line connection region and the word-line connection region.
19 . The semiconductor memory device of claim 18 , wherein the cell array structure further includes:
a plurality of semiconductor patterns that cross the plurality of word lines and are stacked in the direction perpendicular to the first surface of the lower dielectric layer; and
a plurality of data storage elements in contact with first lateral surfaces of the plurality of semiconductor patterns, respectively.
20 . The semiconductor memory device of claim 18 ,
wherein the peripheral circuit structure includes:
a first core region that overlaps the bit-line connection region and includes a plurality of sense amplifiers; and
a second core region that overlaps the word-line connection region and includes a plurality of sub-word line drivers.