Semiconductor memory devices
Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
1. A semiconductor memory device comprising:
a substrate including a cell region and a contact region;
a first stack and a second stack that are on the substrate; and
a first interconnection line and a second interconnection line that are on the first and second stacks,
wherein the first interconnection line extends in a first horizontal direction that is parallel to a top surface of the substrate,
wherein the second interconnection line extends in a second horizontal direction that crosses the first horizontal direction and is parallel to the top surface of the substrate,
wherein each of the first and second stacks comprises:
a plurality of memory cell transistors three-dimensionally arranged on the substrate;
a bit line connected to first ones of the plurality of memory cell transistors, the first ones of the plurality of memory cell transistors being spaced apart from each other in the first horizontal direction; and
a word line connected to second ones of the plurality of memory cell transistors, the second ones of the plurality of memory cell transistors being spaced apart from each other in a vertical direction that is perpendicular to the top surface of the substrate, and
wherein the bit line of the first stack comprises a first bit line, the bit line of the second stack comprises a second bit line, and wherein, on the contact region, the first interconnection line is electrically connected to at least one of the first and second bit lines, and
wherein the word line of the first stack comprises a first word line, the word line of the second stack comprises a second word line, and wherein, on the cell region, the second interconnection line is electrically connected to at least one of the first and second word lines.
2. The semiconductor memory device of claim 1 , wherein the first and second bit lines extend in the first horizontal direction, and
wherein the first and second word lines extend in the vertical direction.
3. The semiconductor memory device of claim 1 , wherein the first bit line and the second bit line are at an equal level.
4. The semiconductor memory device of claim 1 , wherein the substrate further includes a first peripheral circuit region and a second peripheral circuit region,
wherein the first interconnection line extends from the contact region onto the first peripheral circuit region, and
wherein the second interconnection line extends from the cell region onto the second peripheral circuit region.
5. The semiconductor memory device of claim 1 , wherein each of the first and second stacks further comprises a plurality of data storing elements connected to the plurality of memory cell transistors, respectively.
6. The semiconductor memory device of claim 5 , wherein each of the plurality of data storing elements comprises a first electrode, a second electrode and a dielectric layer between the first and second electrodes.
7. The semiconductor memory device of claim 1 , further comprising a third interconnection line on the first and second stacks,
wherein the first interconnection line is electrically connected to the first bit line,
wherein the third interconnection line is electrically connected to the second bit line, and
wherein the second interconnection line is electrically connected to both the first and second word lines.
8. The semiconductor memory device of claim 7 , wherein the second interconnection line extends in the second horizontal direction, and
wherein the first and second word lines are spaced apart from each other in the second horizontal direction and are aligned in the second horizontal direction.
9. The semiconductor memory device of claim 1 , further comprising a third interconnection line on the first and second stacks,
wherein the first interconnection line is electrically connected to both the first and second bit lines,
wherein the second interconnection line is electrically connected to the first word line, and
wherein the third interconnection line is electrically connected to the second word line.
10. The semiconductor memory device of claim 9 , further comprising a common contact contacting both the first and second bit lines,
wherein the first interconnection line is electrically connected to both the first and second bit lines through the common contact.
11. The semiconductor memory device of claim 1 , further comprising:
a first peripheral circuit region and a second peripheral circuit region that are on the substrate,
wherein the first and second stacks are positioned higher than the first and second peripheral circuit regions,
wherein the first interconnection line electrically connects the at least one of the first and second bit lines to the first peripheral circuit region, and
wherein the second interconnection line electrically connects the at least one of the first and second word lines to the second peripheral circuit region.
12. The semiconductor memory device of claim 11 , wherein the first and second bit lines extend in the first horizontal direction, and
wherein the first and second word lines extend in the vertical direction.
13. The semiconductor memory device of claim 11 , wherein each of the first and second stacks further comprises a plurality of data storing elements connected to the plurality of memory cell transistors, respectively.
14. The semiconductor memory device of claim 13 , wherein each of the plurality of data storing elements comprises a first electrode, a second electrode and a dielectric layer between the first and second electrodes.
15. The semiconductor memory device of claim 11 , further comprising:
a first contact electrically connects the first interconnection line to a first peripheral transistor of the first peripheral circuit region; and
a second contact electrically connects the second interconnection line to a second peripheral transistor of the second peripheral circuit region.
16. The semiconductor memory device of claim 1 , further comprising:
a first peripheral transistor and a second peripheral transistor that are on the substrate; and
an interlayered insulating layer on the first and second peripheral transistors,
wherein the interlayered insulating layer is between the substrate and the first and second stacks,
wherein the first interconnection line electrically connects the at least one of the first and second bit lines to the first peripheral transistor, and
wherein the second interconnection line electrically connects the at least one of the first and second word lines to the second peripheral transistor.
17. The semiconductor memory device of claim 16 , wherein the first and second bit lines extend in the first horizontal direction, and
wherein the first and second word lines extend in the vertical direction.
18. The semiconductor memory device of claim 16 , wherein each of the first and second stacks further comprises a plurality of data storing elements connected to the plurality of memory cell transistors, respectively.
19. The semiconductor memory device of claim 18 , wherein each of the plurality of data storing elements comprises a first electrode, a second electrode and a dielectric layer between the first and second electrodes.
20. The semiconductor memory device of claim 16 , further comprising a first contact extends through the interlayered insulating layer and electrically connects the first interconnection line to the first peripheral transistor; and
a second contact extends through the interlayered insulating layer and electrically connects the second interconnection line to the second peripheral transistor.