Multi-chip packages and sinterable paste for use with thermal interface materials
In some embodiments a semiconductor die package includes a package substrate, a plurality of dies each attached to the package substrate, a layer of a thermally conducting sintered paste over the top of each die, a layer of flexible polymer thermal interface material over the sintered paste, and a heat spreader over and thermally connected to the polymer thermal interface material.
1. A semiconductor die package comprising:
a package substrate;
a plurality of dies each attached to the package substrate, the plurality of dies comprising a first die having a first thickness and a second die having a second thickness, the second thickness less than the first thickness;
a first layer of thermally conducting sintered paste over the top of the first die, the first layer of thermally conducting sintered paste having a thickness;
a second layer of thermally conducting sintered paste over the top of the second die, the second layer of thermally conducting sintered paste having a thickness greater than the thickness of the first layer of thermally conducting sintered paste over the top of the first die;
a first layer of flexible polymer thermal interface material over the first layer of thermally conducting sintered paste, the first layer of flexible polymer thermal interface material in direct contact with the first layer of the thermally conducting sintered paste;
a second layer of flexible polymer thermal interface material over the second layer of thermally conducting sintered paste, the second layer of flexible polymer thermal interface material in direct contact with the second layer of the thermally conducting sintered paste; and
a heat spreader over and thermally connected to the first and second layers of polymer thermal interface material.
2. The package of claim 1 , further comprising a lid over the heat spreader.
3. The package of claim 1 , wherein each of the first and second layers of thermally conducting sintered paste has a thermal conductivity greater than 15 W/mK.
4. The package of claim 1 , wherein each of the first and second layers of thermally conducting sintered paste comprises over 50% by weight of a metal filler and a solder alloy to cause the metal filler to sinter.
5. The package of claim 1 , wherein each of the first and second layers of thermally conducting sintered paste comprises an organic binder.
6. The package of claim 1 , wherein each of the first and second layers of thermally conducting sintered paste has a slump no greater than 20% before sintering.
7. The package of claim 1 , wherein the first and second layers of thermally conducting sintered paste have co-planar uppermost surfaces.
8. The package of claim 1 , wherein the first and second layers of polymer thermal interface material have a same thickness.
9. The package of claim 1 , wherein the first layer of polymer thermal interface material is further along sidewalls of the first layer of thermally conducting sintered paste.
10. The package of claim 1 , wherein the second layer of polymer thermal interface material is further along sidewalls of the second layer of thermally conducting sintered paste.
11. The package of claim 1 , wherein the first layer of polymer thermal interface material is further along sidewalls of the first layer of thermally conducting sintered paste, and wherein the second layer of polymer thermal interface material is further along sidewalls of the second layer of thermally conducting sintered paste.