Fan-out semiconductor package
A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads.
1. A fan-out semiconductor package comprising:
a frame including a first insulating layer, a second insulating layer disposed on a first surface of the first insulating layer, a third insulating layer disposed on a second surface of the first insulating layer opposing the first surface, a first wiring layer disposed on the first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers;
a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface;
an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and
a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads,
wherein the first and second wiring layers are electrically connected to the connection pads, and
wherein a surface of the second insulating layer coming in contact with the connection structure is coplanar with a surface of the first wiring layer coming in contact with the connection structure.
2. The fan-out semiconductor package of claim 1 , wherein the second insulating layer and the first wiring layer have the same thickness as each other.
3. The fan-out semiconductor package of claim 1 , wherein a lower surface of the second insulating layer coming in contact with the connection structure and a lower surface of the first wiring layer coming in contact with the connection structure are coplanar with a lower surface of a passivation layer of the semiconductor chip exposing the connection pads.
4. The fan-out semiconductor package of claim 1 , wherein the second wiring layer protrudes on the third insulating layer.
5. The fan-out semiconductor package of claim 1 , wherein the frame further includes through-vias penetrating through the first and third insulating layers and electrically connecting the first and second wiring layers to each other.
6. The fan-out semiconductor package of claim 1 , wherein the first insulating layer has a thickness thicker than those of the second and third insulating layers.
7. The fan-out semiconductor package of claim 6 , wherein the first insulating layer has an elastic modulus greater than those of the second and third insulating layers.
8. The fan-out semiconductor package of claim 1 , further comprising a reinforcing layer disposed on the encapsulant,
wherein the reinforcing layer has an elastic modulus greater than that of the encapsulant.
9. The fan-out semiconductor package of claim 8 , further comprising a resin layer disposed on the reinforcing layer,
wherein the reinforcing layer has the elastic modulus greater than that of the resin layer.
10. The fan-out semiconductor package of claim 9 , further comprising openings penetrating through the resin layer, the reinforcing layer, and the encapsulant and exposing at least portions of the second wiring layer.
11. The fan-out semiconductor package of claim 10 , further comprising a surface treatment layer disposed on a surface of the exposed second wiring layer.
12. The fan-out semiconductor package of claim 1 , further comprising:
a passivation layer disposed on the connection structure and having a plurality of openings exposing at least portions of the redistribution layers, respectively;
a plurality of underbump metal layers disposed on the plurality of openings of the passivation layer, respectively, and connected to the exposed redistribution layers, respectively; and
a plurality of electrical connection structures disposed on the passivation layer, respectively, and connected to the plurality of underbump metal layers, respectively.
13. The fan-out semiconductor package of claim 1 , wherein a portion of an insulating layer of the connection structure has a uniform thickness,
the portion of the insulating layer of the connection structure is in physical contact with the second insulating layer and the first wiring layer.
14. A fan-out semiconductor package comprising:
a frame including a first insulating layer, a second insulating layer disposed on a first surface of the first insulating layer, a third insulating layer disposed on a second surface of the first insulating layer opposing the first surface, a first wiring layer disposed on the first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers;
a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface;
an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and
a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads,
wherein the first and second wiring layers are electrically connected to the connection pads, and
wherein a number of conductor layers of the first wiring layer is larger than a number of conductor layers of the second wiring layer.
15. The fan-out semiconductor package of claim 14 , wherein the first wiring layer includes a first seed layer and a first plating layer, the second wiring layer includes a second seed layer and a second plating layer, and a number of layers of the first seed layer is greater than a number of layers of the second seed layer.
16. A fan-out semiconductor package comprising:
a frame including a first wiring layer embedded in an insulating material so that a lower surface of the first wiring layer is exposed in a lower portion of the frame and a second wiring layer protruding on the insulating material in an upper portion of the frame, and having a through-hole;
a semiconductor chip disposed in the through-hole and having connection pads;
an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole;
a connection structure disposed below the frame and the semiconductor chip and including redistribution layers electrically connected to the connection pads;
a reinforcing layer disposed on the encapsulant; and
a resin layer disposed on the reinforcing layer.