Self-aligned two-dimensional material transistors
View Patent ↗A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.
1. A method of forming a semiconductor device, the method comprising:
forming a structure comprising at least a handle wafer, a two-dimensional (2D) material layer, a gate structure formed on and in contact with the 2D material layer, an insulating layer in contact with the 2D material layer and the gate structure, and a sacrificial layer in contact with the insulating layer and the gate structure;
etching a portion of the sacrificial layer thereby exposing a first portion of the insulating layer;
forming an inter-layer dielectric on the first portion of the insulating layer and sidewalls of the sacrificial layer;
removing the sacrificial layer and a second portion of the insulating layer thereby exposing a portion of the 2D material layer; and
forming a source contact layer and a drain contact layer each in contact with the portion of the 2D material layer.
2. The method of claim 1 , wherein forming the structure comprises:
forming the insulating layer on a top surface of a substrate; and
forming the sacrificial layer on and in contact with the insulating layer.
3. The method of claim 2 , wherein forming the structure further comprises:
forming a trench in the sacrificial layer and the insulating layer thereby exposing a portion of the substrate; and
forming the gate structure within the trench and in contact with the exposed portion of the substrate.
4. The method of claim 3 , wherein forming the gate structure comprises at least:
forming a spacer layer on sidewalls of the trench;
forming a gate dielectric layer in the trench in contact with the exposed portion of the substrate and the spacer layer;
forming a gate conductor layer in contact with at least the gate dielectric layer; and
forming a capping layer in contact with the spacer layer and the gate conductor layer.
5. The method of claim 3 , wherein forming the structure further comprises:
forming a dielectric layer on and in contact with the sacrificial layer and capping laying;
flipping the structure after forming the dielectric layer; and
bonding, after the structure has been flipped, to an intermediary handle wafer.
6. The method of claim 5 , wherein forming the structure further comprises:
removing the substrate after the structure has been bonded to the intermediary handle wafer; and
forming the 2D material layer in contact with the insulating layer and gate structure.
7. The method of claim 6 , wherein forming the structure further comprises:
flipping the structure after forming the 2D material layer;
bonding the structure to the handle wafer after the structure has been flipped; and
removing the intermediary handle wafer.
8. A method of forming a semiconductor device structure, the method comprising:
forming a structure comprising at least a substrate, an insulating layer in contact with the substrate, a sacrificial layer in contact with the insulating layer, and a gate structure in the sacrificial and insulating layers;
flipping the structure and bonding the structure to a first handle wafer;
removing the substrate;
forming a two-dimensional material (2D) layer in contact with the insulating layer and the gate structure;
flipping the structure after the 2D material layer has been formed and bonding the structure to a second handle wafer; and
removing the first handle wafer.
9. The method of claim 8 , further comprising:
etching a portion of the sacrificial layer thereby exposing a first portion of the insulating layer; and
forming an inter-layer dielectric on the first portion of the insulating layer and sidewalls of the sacrificial layer.
10. The method of claim 9 , further comprising:
removing the sacrificial layer and a second portion of the insulating layer thereby exposing a portion of the 2D material layer; and
forming a source contact layer and a drain contact layer each in contact with the portion of the 2D material layer.
11. The method of claim 8 , wherein forming the structure comprises:
forming the insulating layer on a top surface of a substrate; and
forming the sacrificial layer on and in contact with the insulating layer.
12. The method of claim 11 , wherein forming the structure further comprises:
forming a trench in the sacrificial layer and the insulating layer thereby exposing a portion of the substrate; and
forming the gate structure within the trench and in contact with the exposed portion of the substrate.
13. The method of claim 12 , wherein forming the gate structure comprises at least:
forming a spacer layer on sidewalls of the trench;
forming a gate dielectric layer in the trench in contact with the exposed portion of the substrate and the spacer layer;
forming a gate conductor layer in contact with at least the gate dielectric layer; and
forming a capping layer in contact with the spacer layer and the gate conductor layer.
14. The method of claim 13 , further comprising:
forming a dielectric layer on and in contact with the sacrificial layer and capping laying prior to flipping the structure and bonding the structure to the first handle wafer.