Double sense program verification of a memory array

1. A memory device comprising:

a memory array; and

a controller configured to:

execute a non-homogeneous bitline biasing program verify operation on a plurality of bitlines of the memory array;

generate a first count of a number of the bitlines having a particular response to the non-homogeneous bitline biasing program verify operation;

execute a homogeneous bitline biasing program verify operation on the bitlines;

generate a second count of a number of the bitlines having the particular response to the homogeneous bitline biasing program verify operation; and

performing a memory management operation based on the first count and the second count.

2. The memory device of claim 1 , wherein the controller is configured to first execute the non-homogeneous bitline biasing program verify operation, and then execute the homogeneous bitline biasing program verify operation.

3. The memory device of claim 1 , wherein the controller is configured to first execute the homogeneous bitline biasing program verify operation, and then execute the non-homogeneous bitline biasing program verify operation.

4. The memory device of claim 1 , wherein the controller is configured to execute the homogeneous bitline biasing program verify operation only for one particular word line.

5. The memory device of claim 4 , wherein the one particular word line is word line 0.

6. The memory device of claim 1 , wherein the non-homogeneous bitline biasing program verify operation biases bitlines for programmed memory cells to a non-zero-valued first voltage and biases bitlines for erased memory cells to a zero-valued second voltage.

7. The memory device of claim 6 , wherein the homogeneous bitline biasing program verify biases both of the bitlines for erased memory cells and the bitlines for programmed memory cells to the non-zero-valued first voltage.

8. The memory device of claim 6 , wherein the non-zero-valued first voltage is within the range of 0.2V-0.5V.

9. A controller configured to:

execute a non-homogeneous bitline biasing program verify operation on a plurality of bitlines of a memory array;

execute a homogeneous bitline biasing program verify operation on the bitlines; and

compare a first count of a number of the bitlines having a particular response to the non-homogeneous bitline biasing program verify operation with a second count of a number of the bitlines having the particular response to the homogeneous bitline biasing program verify operation.

10. The controller of claim 9 , the controller further configured to execute a memory management operation based on a result of comparing the first count and the second count.

11. The controller of claim 9 , further configured to first execute the non-homogeneous bitline biasing program verify operation, and then execute the homogeneous bitline biasing program verify operation.

12. The controller of claim 9 , further configured to first execute the homogeneous bitline biasing program verify operation, and then execute the non-homogeneous bitline biasing program verify operation.

13. The controller of claim 9 , further configured to execute both of the homogeneous bitline biasing program verify operation and the non-homogeneous bitline biasing program verify operation only for one particular word line.

14. The controller of claim 13 , wherein the one particular word line is word line 0.

15. The controller of claim 9 , wherein the non-homogeneous bitline biasing program verify operation biases bitlines for programmed memory cells to a non-zero-valued first voltage and biases bitlines for erased memory cells to a zero-valued second voltage.

16. The controller of claim 15 , wherein the homogeneous bitline biasing program verify biases both of the bitlines for erased memory cells and the bitlines for programmed memory cells to the non-zero-valued first voltage.

17. The controller of claim 15 , wherein the non-zero-valued first voltage is within the range of 0.2V-0.5V.

18. An apparatus comprising:

memory means;

means for comparing (a) a first count of bitlines of the memory means providing a particular response to a non-homogeneous bitline biasing program verify operation, and (b) a second count of the bitlines responding to a homogeneous bitline biasing program verify operation; and

means for performing a memory management operation based on the comparing.

19. The apparatus of claim 18 , wherein the means for comparing operates only on one particular word line.

20. The apparatus of claim 19 , wherein the one particular word line is word line 0.