IP Library › Granted Patent US 10,910,552
Granted Patent B2
US 10,910,552 · App. 16/352,957 · Granted Feb 2, 2021

Magnetic memory device, method for manufacturing the same, and substrate treating apparatus

Inventors: Joonmyoung Lee (Anyang-si, KR); Yong Sung Park (Suwon-si, KR); Jeong-Heon Park (Hwaseong-si, KR); Hyun Cho (Changwon-si, KR); Ung Hwan Pi (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L43/02G11C14/0036G11C14/0081H01L21/67155H01L27/224H01L27/226H01L43/10H01L43/12G11C11/161H01L27/108H01L27/11
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,910,552
App. No.
16/352,957
Granted
Feb 2, 2021
Kind
B2
Abstract

A magnetic memory device, a method for manufacturing a magnetic memory device, and a substrate treating apparatus, the device including a substrate including a first memory region and a second memory region; a first magnetic tunnel junction pattern on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern on the first free pattern; and a second magnetic tunnel junction pattern on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern on the second free pattern, wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

Claims (40)

1. A magnetic memory device, comprising:

a substrate including a first memory region and a second memory region;

a first magnetic tunnel junction pattern on the first memory region, the first magnetic tunnel junction pattern including a first free pattern and a first oxide pattern on the first free pattern; and

a second magnetic tunnel junction pattern on the second memory region, the second magnetic tunnel junction pattern including a second free pattern and a second oxide pattern on the second free pattern,

wherein a ratio of a thickness of the first oxide pattern to a thickness of the first free pattern is different from a ratio of a thickness of the second oxide pattern to a thickness of the second free pattern.

2. The magnetic memory device of claim 1 , wherein a sum of the thickness of the first oxide pattern and the thickness of the first free pattern is equal to a sum of the thickness of the second oxide pattern and the thickness of the second free pattern.

3. The magnetic memory device of claim 1 , wherein the ratio of the thickness of the first oxide pattern to the thickness of the first free pattern is greater than the ratio of the thickness of the second oxide pattern to the thickness of the second free pattern.

4. The magnetic memory device of claim 3 , wherein:

the first magnetic tunnel junction pattern defines a first memory cell of the first memory region,

the second magnetic tunnel junction pattern defines a second memory cell of the second memory region,

the first memory cell is a non-volatile memory (NVM) cell, and

the second memory cell is a random access memory (RAM) cell.

5. The magnetic memory device of claim 1 , wherein:

the first free pattern is in contact with the first oxide pattern, and

the second free pattern is in contact with the second oxide pattern.

6. The magnetic memory device of claim 1 , wherein an oxygen concentration of the first oxide pattern is higher than an oxygen concentration of the second oxide pattern.

7. The magnetic memory device of claim 1 , wherein the substrate further includes a third memory region, the magnetic memory device further comprising:

a third magnetic tunnel junction pattern on the third memory region, the third magnetic tunnel junction pattern including a third free pattern and a third oxide pattern on the third free pattern,

wherein a ratio of a thickness of the third oxide pattern to a thickness of the third free pattern is:

different from the ratio of the thickness of the first oxide pattern to the thickness of the first free pattern, and

different from the ratio of the thickness of the second oxide pattern to the thickness of the second free pattern.

8. The magnetic memory device of claim 7 , wherein the ratio of the thickness of the third oxide pattern to the thickness of the third free pattern is:

less than the ratio of the thickness of the first oxide pattern to the thickness of the first free pattern, and

greater than the ratio of the thickness of the second oxide pattern to the thickness of the second free pattern.

9. The magnetic memory device of claim 7 , wherein a sum of the thickness of the third oxide pattern and the thickness of the third free pattern is:

equal to a sum of the thickness of the first oxide pattern and the thickness of the first free pattern, and

equal to a sum of the thickness of the second oxide pattern and the thickness of the second free pattern.

10. The magnetic memory device of claim 7 , wherein an oxygen concentration of the third oxide pattern is:

lower than an oxygen concentration of the first oxide pattern, and

higher than an oxygen concentration of the second oxide pattern.

11. The magnetic memory device of claim 7 , wherein:

the first magnetic tunnel junction pattern defines a first memory cell of the first memory region,

the second magnetic tunnel junction pattern defines a second memory cell of the second memory region,

the third magnetic tunnel junction pattern defines a third memory cell of the third memory region,

the first memory cell is a non-volatile memory (NVM) cell,

the second memory cell is a static random access memory (SRAM) cell, and

the third memory cell is a dynamic random access memory (DRAM) cell.

12. The magnetic memory device of claim 1 , wherein:

the first free pattern includes CoFeB, and

the second free pattern includes CoFeB.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2019
From: LEE, JOONMYOUNG; PARK, YONG SUNG; PARK, JEONG-HEON; CHO, HYUN; PI, UNG HWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 048594/0112 →
Priority Claims (1)
KR 10-2018-0111015 · Sep 17, 2018 · national
Continuity (1)
Related Publication 20200091412A1 · Mar 19, 2020
Cited By (3)
US 12,396,178 US 12,495,724 US 12,507,418