Capacitance reduction for semiconductor devices based on wafer bonding

1. A semiconductor device, comprising:

a carrier wafer; and

an integrated circuit (IC) on a device wafer and bonded to the carrier wafer, wherein the IC includes:

a first layer having one or more transistors at a front side of the device wafer, and one or more gaps, wherein each of the one or more transistors comprises a channel structure;

a second layer having a metal interconnect coupled to the one or more transistors;

a capping layer at a backside of the device wafer, filling at least partially the one or more gaps of the first layer, wherein the capping layer is next to the first layer of the device wafer, and wherein the capping layer is in contact with a bottom surface of the channel structure of each of the one or more transistors; and

one or more air gaps formed within the one or more gaps, and between the capping layer and the second layer.

2. The semiconductor device of claim 1 , wherein the IC further includes power wires or bumps coupled to the metal interconnect.

3. The semiconductor device of claim 1 , wherein the capping layer is bonded to the carrier wafer.

4. The semiconductor device of claim 1 , wherein the second layer is bonded to the carrier wafer, the metal interconnect is a first metal interconnect, and the IC further includes a second metal interconnect within the capping layer at the backside of the device wafer.

5. The semiconductor device of claim 1 , wherein the device wafer is bonded to the carrier wafer by direct bonding, surface activated bonding, adhesive bonding, reactive bonding, glass frit bonding, or hybrid bonding.

6. The semiconductor device of claim 1 , wherein the one or more air gaps include an air gap within a gap between a source electrode and a gate electrode of a transistor formed by removing at least a part of a spacer between the source electrode and the gate electrode.

7. The semiconductor device of claim 6 , wherein the transistor further includes a partial spacer between the source electrode and the gate electrode.

8. The semiconductor device of claim 6 , wherein the gap between the source electrode and the gate electrode has a width in a range of about 1 nm to about 2 nm.

9. The semiconductor device of claim 1 , wherein the one or more air gaps include an air gap within a gap formed by removing at least a part of a subfin dielectric layer around a fin of a transistor, an isolation wall of the first layer between the one or more transistors, or a part of an inter-layer dielectric layer of the metal interconnect.

10. The semiconductor device of claim 1 , wherein the IC further includes a low-k dielectric material within the one or more gaps formed by removing components of the one or more transistors, and the low-k dielectric material has a dielectric constant in a range of about 1 to about 3.

11. The semiconductor device of claim 1 , wherein the capping layer includes a low-k dielectric material with a dielectric constant in a range of about 1 to about 3.

12. The semiconductor device of claim 1 , wherein the carrier wafer includes a glass wafer, a sapphire wafer, a polymer wafer, or a silicon wafer.

13. The semiconductor device of claim 1 , wherein the one or more transistors includes a nanowire transistor, a nanotube transistor, a nanoribbon transistor, a FinFET transistor, a tri-gate FinFET transistor, a multiple-gate field-effect transistor (MuGFET) transistor, or a gate-all-around FET transistor.

14. The semiconductor device of claim 1 , wherein the metal interconnect includes metal contacts in multiple metal layers, and vias coupling two metal contacts together.

15. A method for forming a semiconductor device, the method comprising:

forming an integrated circuit (IC) on a device wafer, wherein the IC includes a first layer having one or more transistors at front side of the device wafer, and a second layer having a metal interconnect coupled to the one or more transistors;

coupling the device wafer to a carrier wafer by coupling the second layer of the device wafer to the carrier wafer;

thinning the device wafer at backside of the device wafer to expose the one or more transistors;

removing one or more components of the one or more transistors to form one or more gaps at the first layer; and

forming a capping layer at the backside of the device wafer to fill at least partially the one or more gaps at the first layer, wherein the capping layer is next to the first layer of the device wafer, and wherein the capping layer is in contact with a bottom surface of a channel structure of each of the one or more transistors, and one or more air gaps are formed within the one or more gaps, and between the capping layer and the second layer.

16. The method of claim 15 , wherein the coupling the device wafer to the carrier wafer including temporarily bonding the device wafer to the carrier wafer by a glue layer, and the method further includes:

removing the glue layer between the carrier wafer and the second layer of the device wafer; and

permanently bonding the capping layer with the carrier wafer.

17. The method of claim 15 , wherein the coupling the device wafer to the carrier wafer including permanently bonding the second layer of the device wafer to the carrier wafer, the metal interconnect is a first metal interconnect, and the method further includes:

forming a second metal interconnect within the capping layer at the backside of the device wafer.

18. The method of claim 15 , further comprising:

forming power wires or bumps coupled to the metal interconnect of the second layer.

19. The method of claim 15 , wherein the one or more air gaps include an air gap within a gap between a source electrode and a gate electrode of a transistor formed by removing a spacer between the source electrode and the gate electrode.

20. The method of claim 15 , wherein the one or more air gaps include an air gap within a gap formed by removing at least a part of a subfin dielectric layer around a fin of a transistor, an isolation wall of the first layer between the one or more transistors, or a part of an inter-layer dielectric layer of the metal interconnect.

21. The method of claim 15 , further comprising:

forming a low-k dielectric material within the one or more gaps formed by removing the one or more components of the one or more transistors, and the low-k dielectric material has a dielectric constant in a range of about 1 to about 3.

22. A computing device, comprising:

a print circuit board (PCB); and

a semiconductor device coupled to the PCB, wherein the semiconductor device includes:

a carrier wafer; and

an integrated circuit (IC) on a device wafer and bonded to the carrier wafer, wherein the IC includes:

a first layer having one or more transistors at a front side of the device wafer, and one or more gaps, wherein each of the one or more transistors comprises a channel structure;

a second layer having a metal interconnect coupled to the one or more transistors;

a capping layer at a backside of the device wafer, filling at least partially the one or more gaps of the first layer, wherein the capping layer is next to the first layer of the device wafer, and wherein the capping layer is in contact with a bottom surface of the channel structure of each of the one or more transistors; and

one or more air gaps formed within the one or more gaps, and between the capping layer and the metal interconnect.

23. The computing device of claim 22 , wherein the one or more air gaps include an air gap within a gap formed by removing at least a part of a subfin dielectric layer around a fin of a transistor, an isolation wall of the first layer between the one or more transistors, or a part of an inter-layer dielectric layer of the metal interconnect.

24. The computing device of claim 22 , wherein the IC further includes a low-k dielectric material within the one or more gaps formed by removing components of the one or more transistors, and the low-k dielectric material has a dielectric constant in a range of about 1 to about 3.

25. The computing device of claim 22 , wherein the computing device includes a device selected from the group consisting of a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a display, a battery, a processor, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, and a camera coupled with the memory device.

26. A semiconductor device, comprising:

a carrier wafer; and

an integrated circuit (IC) on a device wafer and bonded to the carrier wafer, wherein the IC includes:

a first layer having one or more transistors at a front side of the device wafer, and one or more gaps formed by removing components of the one or more transistors;

a second layer having a metal interconnect coupled to the one or more transistors;

a capping layer at a backside of the device wafer, filling at least partially the one or more gaps of the first layer, wherein the capping layer is next to the first layer of the device wafer, and wherein the capping layer is in contact with a bottom surface of a channel structure of each of the one or more transistors, wherein the second layer is bonded to the carrier wafer, the metal interconnect is a first metal interconnect, and the IC further includes a second metal interconnect within the capping layer at the backside of the device wafer; and

one or more air gaps formed within the one or more gaps, and between the capping layer and the second layer, wherein the one or more air gaps are to reduce parasitic capacitance of the IC compared to the IC without the one or more air gaps.