IP Library Granted Patent US 10,825,786
Granted Patent B2
US 10,825,786 · App. 16/364,104 · Granted Nov 3, 2020

Polymer resin and compression mold chip scale package

Inventors: Yusheng Lin (Phoenix, AZ); Soon Wei Wang (Seremban, MY); Chee Hiong Chew (Seremban, MY); Francis J. Carney (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L24/02H01L21/561H01L21/568H01L21/6836H01L21/78H01L23/3114H01L23/3185H01L23/544H01L24/03H01L24/05H01L24/13H01L24/94H01L24/96H01L2221/68327H01L2223/5448H01L2223/54406H01L2223/54486H01L2224/024H01L2224/0239H01L2224/02315H01L2224/0346H01L2224/0401H01L2224/05571H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/11334H01L2224/11849H01L2224/131H01L2224/13024H01L2224/94H01L2224/96
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,825,786
App. No.
16/364,104
Granted
Nov 3, 2020
Kind
B2
Abstract

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Claims (29)

1. A chip scale package, comprising:

a die;

a first mold compound contacting a first surface of the die and one or more sidewalls of the die;

a metallization layer coupled on the first surface of the die;

a plurality of solder units coupled on the metallization layer; and

a second mold compound contacting a second surface of the die and one or more sidewalls of the die;

wherein the first mold compound contacts the second mold compound.

2. The package of claim 1 , wherein the first mold compound is selected from a group consisting of: polyimide (PI) and polybenzoxazoles (PBO).

3. The package of claim 1 , wherein the die has at least one stepped side.

4. The package of claim 1 , wherein the one or more sidewalls form one or more planes orthogonal to a plane in which the first surface lies.

5. The package of claim 1 , wherein the second mold compound is compression molded.

6. The package of claim 1 , wherein the plurality of solder units are solder balls.

7. The package of claim 1 , wherein the plurality of solder units are reflowed bumps.

8. The package of claim 1 , wherein the metallization layer is selected from a group consisting of: electroless nickel and gold plating; and copper plating.

9. The package of claim 1 , wherein the second mold compound comprises a material selected from a group consisting of: polyamides, polyimides, polyamide-imides, polyphenylene sulfide (PPS), polyether ether ketone (PEEK), and polyester fiberglass resin.

10. The package of claim 1 , wherein a perimeter of the second mold compound is the same size as a perimeter of the package.

11. A chip scale package, comprising:

a die comprising a first surface and a second surface opposite the first surface;

a first mold compound covering at least a portion of the first surface of the die and one or more sidewalls of the die;

a metallization layer coupled on the first surface of the die; and

a second mold compound covering at least a portion of the second surface of the die and one or more sidewalls of the die;

wherein the first mold compound contacts the second mold compound; and

wherein the one or more sidewalls of the die comprise one or more steps.

12. The package of claim 11 , wherein the wherein the die comprises a thickness less than 250 microns.

13. The package of claim 11 , wherein the first mold compound comprises a polymer resin.

14. The package of claim 11 , wherein the second mold compound is compression molded.

15. The package of claim 11 , wherein the one or more sidewalls are entirely covered by the first mold compound and the second mold compound.

16. The package of claim 11 , wherein a perimeter of the second surface of the die is greater than a perimeter of the first surface of the die.

17. The package of claim 11 , wherein a perimeter of the second mold compound is the same size as a perimeter of the package.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2019
From: LIN, YUSHENG; WANG, SOON WEI; CARNEY, FRANCIS J.; CHEW, CHEE HIONG
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 048693/0598 →
Continuity (2)
Division 15168467 · May 31, 2016
Related Publication 20190221532A1 · Jul 18, 2019