Load/store unit for a processor, and applications thereof

1. A method for processing memory access instructions in a processor that executes instructions out-of-program-order, comprising:

storing a completion buffer identification value for a graduating memory access instruction in a load/store graduation buffer;

using bits of the stored completion buffer identification value to access an entry of a load/store queue associated with the instruction;

retrieving information from the load/store queue entry; and

determining whether to allocate an entry for the instruction in a fill/store buffer based on the retrieved information.

2. The method of claim 1 , further comprising:

allocating an entry for the instruction in the fill/store buffer.

3. The method of claim 2 comprising:

deallocating the entry of the load/store queue associated with the instruction.

4. The method of claim 2 , further comprising:

requesting, using the fill/store buffer, data required for the instruction from the bus interface unit.

5. The method of claim 1 , wherein the retrieving step comprises:

retrieving information about whether data to be loaded in to a register of the processer is available in a data cache.

6. The method of claim 1 , further comprising:

determining whether to allocate an entry for the instruction in a load data queue based on the retrieved information.

7. The method of claim 5 , further comprising:

allocating an entry for the instruction in the load data queue;

storing, using the control logic, an identification value in the entry for the instruction in the load data queue as a pointer between the fill/store buffer and load data queue.

8. A processor that executes instructions out-of-program-order, comprising:

a load/store queue that includes a plurality of entries, each entry of the load/store queue to store information associated with a respective memory access instruction during execution;

a load/store graduation buffer that includes a plurality of entries, each entry of the load/store graduation buffer to store a pointer to a corresponding entry of the load/store queue;

a fill/store buffer that includes a plurality of entries, each entry of the fill/store buffer to store information for a corresponding memory access instruction; and

control logic coupled to the load/store queue, the load/store graduation buffer, and the fill/store buffer and when a pointer in the load/store graduation buffer is serviced and data is not available for the memory access instruction corresponding to the serviced pointer, the control logic is to:

allocate a first entry in the fill/store buffer for the memory access instruction corresponding to the serviced pointer.

9. The processor of claim 8 , wherein the first entry is allocated due to a load or store cache miss.

10. The processor of claim 8 , wherein the fill/store buffer is to request data for the memory access instruction using a bus interface unit.

11. The processor of claim 8 , wherein when required data for the memory access instruction is available in an entry of the fill/store buffer, the fill/store buffer is to forward the data to one or more of:

the load/store queue; a cache; and a load data queue.

12. The processor of claim 8 , wherein the control logic is to deallocate an entry in the load/store queue for the instruction corresponding to the serviced pointer.

13. The processor of claim 8 , wherein the control logic is to:

allocate an entry in a load/data queue for the memory access instruction corresponding to the serviced pointer; and

store an identification value in the entry of the load data queue as a pointer between the first entry in the fill/store buffer and the entry in the load/data queue for the memory access instruction corresponding to the serviced pointer.

14. The processor of claim 8 , wherein the information in each entry of the fill/store buffer includes an identification field; a virtual tag information field; a physical tag information field; and a data field for storing data bits.

15. The processor of claim 14 , wherein the virtual tag information includes one or more of:

a thread context identification value; a virtual address value; a data request value; and a data cache probe request value.

16. The processor of claim 14 , wherein the physical tag information includes one or more of:

a physical address value; and a bus interface unit data returned value.

17. The processor of claim 8 , wherein the fill/store buffer is flushed on a per thread basis and compacted to remove flushed out entries.

18. A tangible computer readable storage medium that includes a processor embodied in software, the processor comprising:

a load/store queue that includes a plurality of entries, each entry of the load/store queue to store information associated with a respective memory access instruction during execution;

a load/store graduation buffer that includes a plurality of entries, each entry of the load/store graduation buffer to store a pointer to a corresponding entry of the load/store queue;

a fill/store buffer that includes a plurality of entries, each entry of the fill/store buffer to store information for a corresponding memory access instruction; and

control logic coupled to the load/store queue, the load/store graduation buffer, and the fill/store buffer and when a pointer in the load/store graduation buffer is serviced and data is not available for the memory access instruction corresponding to the serviced pointer, the control logic is to:

allocate a first entry in the fill/store buffer for the memory access instruction corresponding to the serviced pointer.

19. The tangible computer readable storage medium of claim 18 , wherein the processor is embodied in hardware description language software.

20. The tangible computer readable storage medium of claim 18 , wherein the processor is embodied in one of Verilog hardware description language software and VHDL hardware description language software.