IP Library › Granted Patent US 12,242,925
Granted Patent B2
US 12,242,925 · App. 17/551,923 · Granted Mar 4, 2025

Quantum circuit buffering

Inventors: Jessie Yu (Wappingers Falls, NY); Ryan Woo (Tenafly, NJ); Atsuko Shimizu (Mount Kisco, NY); Kang Bae (Ridgefield, NJ)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06N10/20G06F30/39G06N10/80
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Quick Facts
Patent No.
US 12,242,925
App. No.
17/551,923
Granted
Mar 4, 2025
Kind
B2
Abstract

One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to usage maximization of a physical qubit layout of a quantum computer. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise an identification component that identifies a quantum circuit, and a scheduler component that maps the quantum circuit to a physical qubit layout. In an embodiment, the scheduler component can combine plural quantum circuits, including the quantum circuit into a composite circuit, and map the composite circuit to the physical qubit layout. In an embodiment, an obtaining component can assign the quantum circuit to a temporary storage bucket and can identify whether the temporary storage bucket meets a threshold where the scheduler component can proceed to analyze the quantum circuit.

Claims (47)

1. A system, comprising:

a memory that stores computer executable components; and

a processor that executes at least one of the computer executable components that:

obtains a quantum circuit;

assigns the quantum circuit to a temporary storage bucket; and

in response to determining that the temporary storage bucket meets a defined threshold, maps the quantum circuit to a physical qubit layout of qubits of a quantum system.

2. The system of claim 1 , wherein the at least one of the computer executable components further:

compiles a composite circuit comprising the quantum circuit and at least one other quantum circuit from the temporary storage bucket, and wherein the mapping the quantum circuit comprises mapping the composite circuit to the physical qubit layout instead of the quantum circuit.

3. The system of claim 1 , wherein the mapping is at least partially based on a number of shots of the quantum circuit to be performed.

4. The system of claim 1 , wherein the mapping is at least partially based on a number of gates to be employed to execute the mapping as compared to a number of gates of the quantum circuit prior to execution of the mapping.

5. The system of claim 1 , wherein the mapping is at least partially based on a comparison of execution time of the quantum circuit as compared to a coherency time of the physical qubit layout.

6. The system of claim 1 , wherein the at least one of the computer executable components further:

at least partially based on a variable of the quantum circuit:

assigns a first quantity of physical qubits of the physical qubit layout as a first virtual machine; and

assigns a second quantity of physical qubits of the physical qubit layout as a second virtual machine, and wherein the first quantity is less than or equal to the second quantity.

7. The system of claim 1 , wherein the defined threshold comprises a total quantity of qubits needed for operation of quantum circuits in the temporary storage bucket meeting a defined percentage of the qubits of the quantum system.

8. The system of claim 1 , wherein the defined threshold comprises a defined amount of time that the temporary storage bucket contains at least one quantum circuit.

9. A computer-implemented method, comprising:

identifying, by a system operatively coupled to a processor, a quantum circuit;

mapping, by the system, the quantum circuit to a physical circuit layout of qubits of a quantum system; and

at least partially based on a variable of the quantum circuit, assigning, by the system, a first quantity of the qubits as a first virtual machine and a second quantity of the qubits as a second virtual machine, wherein the first quantity is less than or equal to the second quantity.

10. The computer-implemented method of claim 9 , further comprising:

assigning, by the system, the quantum circuit to a temporary storage bucket.

11. The computer-implemented method of claim 10 , further comprising:

determining, by the system, whether the temporary storage bucket meets a defined threshold such that the mapping, by the system, of the quantum circuit from the temporary storage bucket proceeds.

12. The computer-implemented method of claim 11 , further comprising:

in response to determining that the temporary storage bucket meets the defined threshold:

compiling, by the system, a composite circuit comprising the quantum circuit and at least one other quantum circuit from the temporary storage bucket, and

wherein the mapping the quantum circuit comprises mapping the composite circuit to the physical circuit layout instead of the quantum circuit.

13. The computer-implemented method of claim 9 , wherein the mapping is based at least partially on a number of shots of the quantum circuit to be performed.

14. The computer-implemented method of claim 9 , wherein the mapping is based at least partially on a number of gates to be employed to execute the mapping as compared to a number of gates of the quantum circuit prior to execution of the mapping.

15. The computer-implemented method of claim 9 , wherein the mapping is based at least partially on a comparison of execution time of the quantum circuit as compared to a coherency time of the physical qubit layout.

16. A computer program product facilitating a process to buffer one or more quantum circuits, the computer program product comprising a non-transitory computer readable medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

identify, by the processor, a quantum circuit; and

map, by the processor, the quantum circuit to a physical qubit layout of qubits of a quantum system based at least partially on at least one of a number of shots of the quantum circuit to be performed, a number of gates to be employed to execute the mapping as compared to a number of gates of the quantum circuit prior to execution of the mapping, or a comparison of execution time of the quantum circuit as compared to a coherency time of the physical qubit layout.

17. The computer program product of claim 16 , wherein the program instructions are further executable by the processor to cause the processor to:

assign, by the processor, the quantum circuit to a temporary storage bucket.

18. The computer program product of claim 17 , wherein the program instructions are further executable by the processor to cause the processor to:

determine, by the processor, whether the temporary storage bucket meets a defined threshold such that, the mapping of the quantum circuit from the temporary storage bucket proceeds.

19. The computer program product of claim 18 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to determining that the temporary storage bucket meets the defined threshold:

compile, by the processor, a composite circuit comprising the quantum circuit and at least one other quantum circuit from the temporary storage bucket, and

wherein the mapping the quantum circuit comprises mapping the composite circuit to the physical qubit layout instead of the quantum circuit.

20. The computer program product of claim 16 , wherein the program instructions are further executable by the processor to cause the processor to:

at least partially based on a variable of the quantum circuit:

assign, by the processor, a first quantity of the qubits as a first virtual machine; and

assign, by the processor, a second quantity of the qubits as a second virtual machine, wherein the first quantity is less than or equal to the second quantity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2021
From: YU, JESSIE; WOO, RYAN; SHIMIZU, ATSUKO; BAE, KANG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 058400/0247 →
Continuity (1)
Related Publication 20230186130A1 · Jun 15, 2023
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