Re-generation of a gate-level quantum circuit based on gate-level analysis

1. A method to be implemented at a functional-level processing component, the method comprising:

obtaining a functional-level representation of a quantum circuit, wherein the functional-level representation comprises a functional block that defines an operation of the quantum circuit over at least two cycles;

synthesizing a gate-level representation of the quantum circuit based on the functional-level representation of the quantum circuit, wherein the gate-level representation of the quantum circuit comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation of the quantum circuit comprises a first sub-circuit and a second sub-circuit;

providing the gate-level representation to a gate-level processing component;

obtaining a change indication from the gate-level processing component, the change indication indicating that the gate-level processing component modified the first sub-circuit, whereby determining a modified first sub-circuit;

in response to the change indication, synthesizing a modified second sub-circuit based on a knowledge of an existence of the modified first sub-circuit, whereby a second gate-level representation of the quantum circuit is determined, the second gate-level representation of the quantum circuit comprises the modified first sub-circuit and the modified second sub-circuit.

2. The method of claim 1 , wherein the change indication comprises an indication of resources utilized by the modified first sub-circuit.

3. The method of claim 2 , wherein the resources utilized by the modified first sub-circuit comprise a number of qubits utilized by the modified first sub-circuit, wherein the number of qubits utilized by the modified first sub-circuit is smaller than a number of qubits utilized by the first sub-circuit, whereby qubit resources are freed to be utilized in said synthesizing the modified second sub-circuit.

4. The method of claim 2 , wherein the resources utilized by the modified first sub-circuit comprise a number of cycles included in the modified first sub-circuit, wherein the number of cycles included in the modified first sub-circuit is smaller than a number of cycles included in the first sub-circuit, whereby cycle resources are freed to be utilized in said synthesizing the modified second sub-circuit.

5. The method of claim 2 , wherein the resources utilized by the modified first sub-circuit comprise a number of cycles included in the modified first sub-circuit, wherein the number of cycles included in the modified first sub-circuit is larger than a number of cycles included in the first sub-circuit, wherein a set of one or more qubits is idle during at least one cycle of the modified first sub-circuit, whereby parallel execution during the at least one cycle is enabled.

6. The method of claim 1 , wherein said synthesizing the gate-level representation of the quantum circuit is performed using a model of the quantum circuit, wherein said synthesizing the modified second sub-circuit is performed using a modified model of the quantum circuit in which the modified first sub-circuit is an invariant.

7. The method of claim 6 , wherein a gate-level representation of the invariant is included in the modified model.

8. The method of claim 6 , wherein the modified first sub-circuit is a black box whose implementation details are devoid from the modified model, wherein the modified model includes resource utilization of the modified first sub-circuit.

9. The method of claim 8 , wherein the resource utilization of the modified first sub-circuit comprises a number of qubits allocated for the modified first sub-circuit and a number of cycles during which the modified first sub-circuit operates.

10. The method of claim 1 , wherein the second sub-circuit comprises a first implementation of the functional block, wherein the modified second sub-circuit comprises a second implementation of the functional block requiring a different number of qubits or cycles, whereby a resource utilization of the second gate-level representation of the quantum circuit is a Pareto improvement over a resource utilization of the gate-level representation of the quantum circuit.

11. The method of claim 1 , wherein said synthesizing the modified second sub-circuit comprises:

determining a functional-level representation of the second sub-circuit; and

synthesizing the modified second sub-circuit based on the functional-level representation of the second sub-circuit and based on the knowledge of an existence of the modified first sub-circuit.

12. An apparatus comprising a processor and coupled memory, said processor being adapted to perform, at a functional-level processing component, the steps of:

obtaining a functional-level representation of a quantum circuit, wherein the functional-level representation comprises a functional block that defines an operation of the quantum circuit over at least two cycles;

synthesizing a gate-level representation of the quantum circuit based on the functional-level representation of the quantum circuit, wherein the gate-level representation of the quantum circuit comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation of the quantum circuit comprises a first sub-circuit and a second sub-circuit;

providing the gate-level representation to a gate-level processing component;

obtaining a change indication from the gate-level processing component, the change indication indicating that the gate-level processing component modified the first sub-circuit, whereby determining a modified first sub-circuit;

in response to the change indication, synthesizing a modified second sub-circuit based on a knowledge of an existence of the modified first sub-circuit, whereby a second gate-level representation of the quantum circuit is determined, the second gate-level representation of the quantum circuit comprises the modified first sub-circuit and the modified second sub-circuit.

13. The apparatus of claim 12 , wherein the change indication comprises an indication of resources utilized by the modified first sub-circuit.

14. The apparatus of claim 13 , wherein the resources utilized by the modified first sub-circuit comprise a number of qubits utilized by the modified first sub-circuit, wherein the number of qubits utilized by the modified first sub-circuit is smaller than a number of qubits utilized by the first sub-circuit, whereby qubit resources are freed to be utilized in said synthesizing the modified second sub-circuit.

15. The apparatus of claim 13 , wherein the resources utilized by the modified first sub-circuit comprise a number of cycles included in the modified first sub-circuit, wherein the number of cycles included in the modified first sub-circuit is smaller than a number of cycles included in the first sub-circuit, whereby cycle resources are freed to be utilized in said synthesizing the modified second sub-circuit.

16. The apparatus of claim 13 , wherein the resources utilized by the modified first sub-circuit comprise a number of cycles included in the modified first sub-circuit, wherein the number of cycles included in the modified first sub-circuit is larger than a number of cycles included in the first sub-circuit, wherein a set of one or more qubits is idle during at least one cycle of the modified first sub-circuit, whereby parallel execution during the at least one cycle is enabled.

17. The apparatus of claim 12 , wherein said synthesizing the gate-level representation of the quantum circuit is performed using a model of the quantum circuit, wherein said synthesizing the modified second sub-circuit is performed using a modified model of the quantum circuit in which the modified first sub-circuit is an invariant.

18. The apparatus of claim 17 , wherein a gate-level representation of the invariant is included in the modified model.

19. The apparatus of claim 17 , wherein the modified first sub-circuit is a black box whose implementation details are devoid from the modified model, wherein the modified model includes resource utilization of the modified first sub-circuit.

20. A computer program product comprising a non-transitory computer readable medium retaining program instructions, which program instructions when read by a processor, cause the processor to perform, at a functional-level processing component, the steps of:

obtaining a functional-level representation of a quantum circuit, wherein the functional-level representation comprises a functional block that defines an operation of the quantum circuit over at least two cycles;

synthesizing a gate-level representation of the quantum circuit based on the functional-level representation of the quantum circuit, wherein the gate-level representation of the quantum circuit comprises a set of quantum gates defining operations on a set of qubits, wherein the gate-level representation of the quantum circuit comprises a first sub-circuit and a second sub-circuit;

providing the gate-level representation to a gate-level processing component;

obtaining a change indication from the gate-level processing component, the change indication indicating that the gate-level processing component modified the first sub-circuit, whereby determining a modified first sub-circuit;

in response to the change indication, synthesizing a modified second sub-circuit based on a knowledge of an existence of the modified first sub-circuit, whereby a second gate-level representation of the quantum circuit is determined, the second gate-level representation of the quantum circuit comprises the modified first sub-circuit and the modified second sub-circuit.