IP Library › Granted Patent US 11,616,057
Granted Patent B2
US 11,616,057 · App. 16/367,144 · Granted Mar 28, 2023

IC including back-end-of-line (BEOL) transistors with crystalline channel material

Inventors: Prashant Majhi (San Jose, CA); Abhishek Sharma (Hillsboro, OR); Brian Doyle (Portland, OR); Ravi Pillarisetty (Portland, OR); Willy Rachmady (Beaverton, OR)
Assignee: Intel Corporation
H01L27/0688H01L21/02645H01L21/02667H01L23/528H01L29/267
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Quick Facts
Patent No.
US 11,616,057
App. No.
16/367,144
Granted
Mar 28, 2023
Kind
B2
Abstract

IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

Claims (30)

1. An integrated circuit (IC) structure, comprising:

a first device level comprising a first transistor, the first transistor comprising a substantially monocrystalline first material;

a second device level comprising a plurality of second transistors having a lateral pitch of 100 nm, or less, within an area surrounding a plurality of seed structures having a lateral pitch of at least 1 μm, wherein the seed structures comprise a crystalline second material, and wherein each of the plurality of second transistors comprise a third material having a different composition than that of the second material, and having a crystallinity associated with a crystal grain of the second material;

a dielectric material between the first device level and the second device level; and

one or more interconnect metallization levels coupled to terminals of the first transistor and the second transistors.

2. The IC structure of claim 1 , wherein the second material has a higher melting temperature than the third material.

3. The IC structure of claim 1 , wherein the third material is either substantially monocrystalline or comprises a plurality of grains that have a texture associated with the crystal grain of the second material.

4. The IC structure of claim 1 , wherein:

the second device level comprises a third transistor comprising the third material; and

the third material of the second transistors has the same crystallinity as the third material of the third transistor.

5. The IC structure of claim 4 , wherein the second material is in contact with the first material, and the third material is epitaxial to the first material.

6. The IC structure of claim 1 , wherein:

the second device level comprises a third transistor comprising the third material; and

the third material of the second transistors has different crystallinity than the third material of the third transistor.

7. The IC structure of claim 6 , wherein the second material is separated from the first device level by the dielectric material.

8. The IC structure of claim 7 , wherein:

the seed structure is a first seed structure, and the second device level further comprises a second seed structure comprising the second material;

the second material of the first seed structure has different crystallinity than that of the second material of the second seed structure;

the third material of the second transistors has the same crystallinity as that of the second material of the first seed structure; and

the third material of the third transistor has the same crystallinity as that of the second material of the second seed structure.

9. The IC structure of claim 1 , wherein the second material comprises a metal, a metal nitride, or a semiconductor.

10. The IC structure of claim 9 , wherein the second material comprises at least one of Ti, Al, or nitrogen.

11. The IC structure of claim 9 , wherein the first material comprises silicon and the second material comprises more Ge than the first material.

12. The IC structure of claim 11 , wherein the third material has a different composition than the first material.

13. The IC structure of claim 12 , wherein the third material is a group III-V semiconductor comprising at least one of In, Ga, and As.

14. A computer platform, comprising:

a power supply; and

a three-dimensional integrated circuit (3DIC) coupled to receive power from the power supply, wherein the 3DIC further comprises the IC structure of claim 1 .

15. The computer platform of claim 14 , further comprising at least one of a wireless radio or a display.

16. The computer platform of claim 15 , wherein the first material comprises silicon, the second material comprises germanium and the third material comprises an alloy of Group III element, and a Group IV element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2019
From: MAJHI, PRASHANT; SHARMA, ABHISHEK; DOYLE, BRIAN; PILLARISETTY, RAVI; RACHMADY, WILLY
To: INTEL CORPORATION
Reel/Frame 050223/0835 →
Continuity (1)
Related Publication 20200312839A1 · Oct 1, 2020
Cited By (1)
US 12,725,646