Ferroelectric in-memory computing
A computer program product for training a machine learning model. A processor executes program instructions stored on a computer readable media to perform a forward pass read by applying a bias input voltage to a gate of a first resistive processing unit (RPU) configured for infrequent writes and storing a first conductance value representing a synaptic weight value to read from the first RPU a product of the bias input voltage and the first conductance value. The processor performs a backward pass to compute a loss value for the forward pass read and to compute a gradient value to minimize the loss value. The processor applies a coercive input voltage to a gate of a second RPU configured differently for frequent writes to write to the second RPU a second conductance value related to the gradient value and representing a gradient accumulation value.
1 . A resistive processing unit (RPU) system configured to perform in-memory computing operations for training a machine learning model, the RPU system comprising:
a crossbar array of row control lines intersecting column control lines; and
a plurality of non-volatile resistive memory elements, each connected to one of the row control lines and to one of the column control lines, each non-volatile resistive memory element comprising:
a first ferroelectric field-effect-transistor (FeFET) configured to store a first conductance value that represents a synaptic weight value for the machine learning model; and
a second FeFET configured to store a second conductance value that represents a gradient accumulation value for the machine learning model.
2 . The RPU system of claim 1 , wherein:
the first FeFET comprises:
a first semiconductor substrate, comprising:
a first source region;
a first drain region; and
a first channel region between the first source and first drain regions;
a first ferroelectric layer; and
an interfacial layer between the first channel region and the first ferroelectric layer; and
the second FeFET comprises:
a second semiconductor substrate, comprising:
a second source region;
a second drain region; and
a second channel region between the second source and second drain regions; and
a second ferroelectric layer,
wherein there is no interfacial layer between the second channel region and the second ferroelectric layer.
3 . The RPU system of claim 2 , wherein the first FeFET and the second FeFET are vertically integrated on the first semiconductor substrate and the second semiconductor substrate.
4 . The RPU system of claim 2 , further comprising a first connecting circuit electrically connecting the first source region to the second source region.
5 . The RPU system of claim 4 , further comprising:
a first gate electrode layer on the first ferroelectric layer;
a second gate electrode layer on the second ferroelectric layer, wherein:
at least one of the first source region and the second source region is configured to be connected to a source line;
the first gate electrode layer is configured to be connected to a first gate line;
the second gate electrode layer is configured to be connected to a second gate line;
the first drain region is configured to be connected to a first drain line; and
the second drain region is configured to be connected to a second drain line.
6 . The RPU system of claim 2 , further comprising a second connecting circuit electrically connecting the first drain region to the second drain region.
7 . The RPU system of claim 6 , further comprising:
a first gate electrode layer on the first ferroelectric layer; and
a second gate electrode layer on the second ferroelectric layer, wherein:
at least one of the first source region and the second source region is configured to be connected to a source line;
the first gate electrode layer is configured to be connected to a first gate line;
the second gate electrode layer is configured to be connected to a second gate line; and
at least one of the first drain region and the second drain region is configured to be connected to a drain line.