In-transistor load modulation

1. A power amplifier, comprising:

a semiconductor die comprising a main amplifier including a first transistor, and a peaking amplifier including a second transistor having at least one characteristic different than the first transistor,

wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors,

wherein the semiconductor die further comprises a transmission line that electrically connects respective inputs or respective outputs of the main amplifier and the peaking amplifier,

wherein the transmission line comprises a conductive segment extending on the semiconductor die, and a length of the conductive segment extending on the semiconductor die is configured to provide signals to the respective inputs or signals from the respective outputs with a predetermined phase shift therebetween based on a frequency component of an input signal.

2. A power amplifier, comprising:

a semiconductor die comprising a main amplifier including a first transistor, and a peaking amplifier including a second transistor having at least one characteristic different than the first transistor,

wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors,

wherein the semiconductor die further comprises an input transmission line that electrically connects respective inputs of the main and the peaking amplifiers on the semiconductor die to provide an input signal thereto, and an output transmission line that electrically connects respective outputs of the main and the peaking amplifiers on the semiconductor die,

wherein the respective gates of the first and second transistors comprise respective elongated gate fingers, and wherein the input transmission line comprises a gate runner that electrically connects the respective elongated gate fingers of the first and second transistors to provide the common gate bias thereto, and

wherein at least one of the input transmission line or the output transmission line comprises an electrical length that is configured to provide signals to the respective inputs or signals from the respective outputs, respectively, with a predetermined phase shift therebetween based on a frequency component of the input signal.

3. The power amplifier of claim 2 , wherein the first and second transistors further comprise respective elongated drain contacts extending between pairs of the respective elongated gate fingers, and wherein the output transmission line comprises a drain runner that electrically connects the respective elongated drain contacts of the first and second transistors.

4. The power amplifier of claim 3 , wherein:

the electrical length of the input transmission line is defined by a portion of the gate runner that extends between the respective elongated gate fingers of the first and second transistors; and/or

the electrical length of the output transmission line is defined by a portion of the drain runner that extends between the respective elongated drain contacts of the first and second transistors.

5. The power amplifier of claim 4 , wherein the portion of the gate runner and/or or the portion of the drain runner is free of electrical connections to the first and second transistors.

6. The power amplifier of claim 4 , wherein the respective elongated gate fingers of the first and second transistors are connected to the gate runner by first and second gate buses at opposite ends of the portion of the gate runner, respectively, and the respective elongated drain contacts of the first and second transistors are connected to the drain runner by first and second drain buses at opposite ends of the portion of the drain runner, respectively.

7. The power amplifier of claim 2 , wherein the respective elongated gate fingers of the first transistors comprise different materials, different dopant concentrations, different thicknesses, and/or different depths relative to respective channel regions thereof than the respective elongated gate fingers of the second transistors on the semiconductor die.

8. The power amplifier of claim 1 , wherein the length comprises one quarter of a wavelength corresponding to a frequency component of the input signal.

9. The power amplifier of claim 2 wherein at least one of the input transmission line or the output transmission line comprises a distributed element circuit on the semiconductor die and is free of lumped elements.

10. A power amplifier, comprising:

a semiconductor die comprising a main amplifier including a first transistor having a first threshold voltage, and a peaking amplifier including a second transistor having a second threshold voltage that is different than the first threshold voltage,

wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors,

wherein, based on the common gate bias, the first and second transistors on the semiconductor die are configured to turn on in sequence responsive to different power levels of an input signal to the power amplifier, and

wherein the semiconductor die further comprises a third amplifier including a third transistor having a third threshold voltage that is different than the first and second threshold voltages.

11. The power amplifier of claim 10 , wherein the third amplifier comprises a driver amplifier having an input configured to receive the input signal to the power amplifier and an output coupled to one or more of the respective gates of the first or second transistors.

12. A method of fabricating a power amplifier, the method comprising:

forming a semiconductor die comprising a main amplifier including a first transistor and a peaking amplifier including a second transistor having at least one characteristic different than the first transistor,

wherein the peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors of the semiconductor die,

wherein the semiconductor die further comprises a transmission line that electrically connects respective inputs or respective outputs of the main amplifier and the peaking amplifier,

wherein the transmission line comprises a conductive segment extending on the semiconductor die, and a length of the conductive segment extending on the semiconductor die is configured to provide signals to the respective inputs or signals from the respective outputs with a predetermined phase shift therebetween based on a frequency component of an input signal.

13. A semiconductor device, comprising:

a semiconductor die;

a first amplifier on the semiconductor die, the first amplifier comprising a plurality of first transistors having a first threshold voltage and comprising first gate fingers;

a second amplifier on the semiconductor die, the second amplifier comprising a plurality of second transistors having a second threshold voltage different than the first threshold voltage and comprising second gate fingers; and

a gate runner on the semiconductor die, the gate runner electrically connecting the first gate fingers and the second gate fingers to apply a common gate bias to the first and second amplifiers,

wherein a portion of the gate runner extending between the first gate fingers and the second gate fingers comprises an electrical length that is based on a frequency component of a radio frequency (RF) input signal to the first and second amplifiers.

14. The semiconductor device of claim 13 , wherein, based on the common gate bias, the first and second amplifiers are configured to turn on in sequence responsive to different power levels of the RF input signal.

15. The semiconductor device of claim 13 , further comprising:

a drain runner on the semiconductor die, the drain runner electrically connecting first drain fingers of the first transistors and second drain fingers of the second transistors,

wherein a portion of the drain runner extending between the first drain fingers and the second drain fingers comprises the electrical length.

16. The semiconductor device of claim 15 , wherein the portion of the gate runner and/or or the portion of the drain runner is free of electrical connections to the first and second transistors.

17. The semiconductor device of claim 15 , wherein the first and second gate fingers are connected to the gate runner by first and second gate buses at opposite ends of the portion of the gate runner, respectively, and the first and second drain fingers are connected to the drain runner by first and second drain buses at opposite ends of the portion of the drain runner, respectively.

18. The semiconductor device of claim 15 , wherein the electrical length comprises one quarter of a wavelength corresponding to the frequency component of the RF input signal.

19. The semiconductor device of claim 15 , wherein at least one of the gate runner or the drain runner comprises a distributed element circuit on the semiconductor die and is free of lumped elements.

20. The semiconductor device of claim 13 , wherein the first gate fingers of the first transistors comprise different materials, different dopant concentrations, different thicknesses, and/or different depths relative to respective channel regions thereof than the second gate fingers of the second transistors on the semiconductor die.

21. The semiconductor device of claim 13 , wherein the semiconductor die further comprises a third amplifier including a plurality of third transistors having a third threshold voltage that is different from the first and second threshold voltages.

22. The semiconductor device of claim 21 , wherein the third amplifier comprises a driver amplifier having an input configured to receive the RF input signal and an output coupled to one or more of the first or second gate fingers.

23. The semiconductor device of claim 13 , wherein the plurality of the second transistors is greater in number than the plurality of the first transistors.

24. The semiconductor device of claim 13 , wherein the plurality of the first and second transistors comprise high electron mobility transistors (HEMTs) or metal-oxide-semiconductor field effect transistors (MOSFETs).

25. The method of claim 12 , wherein, based on the common gate bias, the first and second transistors on the semiconductor die are configured to turn on in sequence responsive to different power levels of the input signal to the power amplifier.

26. The method of claim 25 , wherein the first and second transistors have different first and second threshold voltages, respectively.

27. The method of claim 12 , wherein the transmission line is an input transmission line that electrically connects respective inputs of the main and the peaking amplifiers on the semiconductor die to provide the input signal thereto.

28. The method of claim 27 , wherein the transmission line is an output transmission line that electrically connects respective outputs of the main and the peaking amplifiers on the semiconductor die.

29. The method of claim 28 , wherein the respective gates of the first and second transistors comprise respective elongated gate fingers, and wherein the input transmission line comprises a gate runner that electrically connects the respective elongated gate fingers of the first and second transistors to provide the common gate bias thereto.

30. The method of claim 29 , wherein the first and second transistors further comprise respective elongated drain contacts extending between pairs of the respective elongated gate fingers, and wherein the output transmission line comprises a drain runner that electrically connects the respective elongated drain contacts of the first and second transistors.

31. The method of claim 26 , wherein forming the semiconductor die comprises forming the respective gates of the first transistors with different materials, different dopant concentrations, different thicknesses, and/or different depths relative to respective channel regions thereof than the respective gates of the second transistors on the semiconductor die.

32. The method of claim 12 , wherein forming the semiconductor die comprises singulating the semiconductor die comprising the main amplifier and the peaking amplifier thereon from a semiconductor wafer.