Dual mode snap back circuit device
A dual mode snap back circuit device is disclosed. The dual mode snap back device may be used for electrostatic discharge (ESD) protection, and may provide both positive ESD protection and negative ESD protection. The dual mode snap back device may implement both an n-type metal-oxide-semiconductor (NMOS) transistor (e.g., a gate-grounded NMOS transistor, such as a gate-grounded extended drain NMOS (GGEDNMOS) transistor) to provide protection against positive ESD events and a bipolar junction transistor (BJT) (e.g., a PNP BJT) to provide protection against negative ESD events. Other embodiments may be described and claimed.
1. A circuit comprising:
a signal pad; and
a dual mode snap back device coupled to the signal pad, the dual mode snap back device to implement a PNP bipolar junction transistor (BJT) and an n-type metal-oxide-semiconductor (NMOS) transistor, wherein the dual mode snap back device includes:
a first p-type region on a substrate, wherein the first p-type region is an emitter of the PNP BJT;
a first n-type region on an N-well, wherein the first n-type region is a base of the PNP BJT and a drain of the NMOS transistor;
a second n-type region on a P-well, wherein the second n-type region is a source of the NMOS transistor; and
a second p-type region between the first and second n-type regions, wherein the second p-type region is a collector of the PNP BJT;
wherein the first n-type region and the second p-type region are conductively coupled to the signal pad; and
wherein the first p-type region and the second n-type region are conductively coupled to a ground terminal.
2. The circuit of claim 1 , further comprising a gate region over the N-well and the P-well, wherein the gate region is a gate of the NMOS, and wherein the gate region is conductively coupled to the ground terminal.
3. The circuit of claim 1 , wherein the second p-type region is on a third p-type region that is in the N-well, wherein the third p-type region is more lightly doped than the second p-type region.
4. The circuit of claim 1 , wherein the dual mode snap back device further comprises a deep N-well below the N-well, wherein the deep N-well is doped differently than the N-well.
5. The circuit of claim 1 , wherein the substrate is a p-type substrate.
6. The circuit of claim 1 , wherein the P-well is adjacent to the N-well, and wherein the first p-type region is on a portion of the substrate that is adjacent to the P-well.
7. The circuit of claim 1 , wherein the NMOS transistor is a gate-grounded extended drain NMOS (GGEDNMOS) transistor.
8. The circuit of claim 1 , wherein the NMOS transistor is to enter a snapback mode in response to a positive electrostatic discharge (ESD) stress on the signal pad, and wherein the PNP BJT is to enter a snapback mode in response to a negative ESD stress on the signal pad.
9. A dual mode snap back circuit device comprising:
a first p-type region on a substrate, wherein the first p-type region is an emitter of a PNP BJT;
a first n-type region on an N-well, wherein the first n-type region is a base of the PNP BJT and a drain of a gate-grounded extended drain n-type metal-oxide-semiconductor (GGEDNMOS) transistor;
a second n-type region on a P-well, wherein the second n-type region is a source of the GGEDNMOS transistor;
a second p-type region between the first and second n-type regions, wherein the second p-type region is a collector of the PNP BJT, wherein the second p-type region is on a third p-type region that is in the N-well, and wherein the third p-type region is more lightly doped than the second p-type region; and
a gate region between the second n-type region and the second p-type region, wherein the gate region is the gate of the GGEDNMOS transistor.
10. The device of claim 9 ,
wherein the first n-type region and the second p-type region are conductively coupled to a node that is to be protected from ESD stress; and
wherein the first p-type region, the second n-type region, and the gate region are conductively coupled to a ground terminal.
11. The device of claim 10 , wherein the GGEDNMOS transistor is to enter a snapback mode in response to a positive ESD stress on the node, and wherein the PNP BJT is to enter a snapback mode in response to a negative ESD stress on the node.
12. The device of claim 9 , wherein the gate region is over the N-well and the P-well.
13. The device of claim 9 , further comprising a deep N-well below the N-well, wherein the deep N-well is doped differently than the N-well.
14. The device of claim 9 , wherein the substrate is a p-type substrate.
15. The device of claim 9 , wherein the P-well is adjacent to the N-well, and wherein the first p-type region is on a portion of the substrate that is adjacent to the P-well.
16. A computing system comprising:
a motherboard; and
an integrated circuit (IC) die coupled to the motherboard, the IC die including:
an input/output (I/O) pad; and
a dual mode snap back device coupled to a signal pad, the dual mode snap back device to implement a PNP bipolar junction transistor (BJT) and an n-type metal-oxide-semiconductor (NMOS) transistor, wherein the dual mode snap back device includes:
a first p-type region that is an emitter of the PNP BJT;
a first n-type region that is a base of the PNP BJT and a drain of the NMOS transistor;
a second n-type region between the first p-type region and the first n-type region, wherein the second n-type region is a source of the NMOS transistor;
a second p-type region between the first and second n-type regions, wherein the second p-type region is a collector of the PNP BJT; and
a gate region between the second n-type region and the second p-type region, wherein the gate region is a gate of the NMOS transistor;
wherein the first n-type region and the second p-type region are conductively coupled to the I/O pad; and
wherein the first p-type region, the second n-type region, and the gate region are conductively coupled to a ground terminal.
17. The computing system of claim 16 , wherein:
the first p-type region is on a p-type substrate;
the first n-type region is on an N-well;
the second n-type region is on a P-well;
the second p-type region is on a third p-type region, wherein the third p-type region is in the N-well and is more lightly doped than the second p-type region; and
the gate region is over the P-well and the N-well.
18. The computing system of claim 17 , wherein the dual mode snap back device further comprises a deep N-well below the N-well, wherein the deep N-well is doped differently than the N-well.
19. The computing system of claim 16 , wherein the NMOS transistor is a gate-grounded extended drain NMOS (GGEDNMOS) transistor.
20. The computing system of claim 16 , wherein the NMOS transistor is to enter a snapback mode in response to a positive ESD stress on the I/O pad, and wherein the PNP BJT is to enter a snapback mode in response to a negative ESD stress on the I/O pad.
21. The computing system of claim 16 , further comprising one or more of a memory circuit, a communication chip, an antenna, or a display coupled to the IC die.