Method of manufacturing semiconductor devices
In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.
1. A pattern forming method for a semiconductor device, the method comprising:
forming a first opening in an underlying layer disposed over a substrate;
expanding the first opening in a first axis by directional etching to form a first groove in the underlying layer;
forming a resist pattern over the underlying layer, the resist pattern including a second opening only partially overlapping the first groove; and
patterning the underlying layer by using the resist pattern as an etching mask to form a second groove.
2. The pattern forming method of claim 1 , wherein in the expanding the first opening, an expanding amount in one direction along the first axis is equal to an extending amount in another direction opposite to the one direction along the first axis.
3. The pattern forming method of claim 1 , wherein in the directional etching, an etching rate of the underlying layer along the first axis is greater than an etching rate of the underlying layer along a second axis perpendicular to the first axis.
4. The pattern forming method of claim 3 , wherein the etching rate of the underlying layer along the first axis is twice or more the etching rate of the underlying layer along the second axis perpendicular to the first axis.
5. The pattern forming method of claim 1 , wherein:
the underlying layer includes a first layer and a second layer formed over the first layer,
the first opening is formed in the first layer and the second layer, and
in the patterning the underlying layer, the second layer is patterned to form the second groove in the second layer.
6. The pattern forming method of claim 5 , wherein the first layer and the second layer are made of different dielectric materials from each other.
7. The pattern forming method of claim 5 , wherein the resist pattern fills the first opening formed in the first layer so that the second opening does not overlap the first opening formed in the first layer.
8. The pattern forming method of claim 1 , wherein the first opening has a circular shape in plan view.
9. A method of manufacturing a semiconductor device, the method comprising:
forming a first underlying layer over a substrate and a second underlying layer over the first underlying layer;
forming a first opening and a second opening in the first and second underlying layers;
expanding the first opening and the second opening in a first axis by directional etching to form a first groove and a second groove in the second underlying layer;
forming a resist pattern including a third opening only partially overlapping the first groove and a fourth opening only partially overlapping the second groove;
patterning the second underlying layer by using the resist pattern as an etching mask to form a first trench and a second trench in the second underlying layer; and
filling the first and second openings formed in the first underlying layer and the first and second trenches formed in the second underlying layer with conductive material.
10. The method of claim 9 , wherein in the directional etching, an etching rate of the second underlying layer along the first axis is greater than an etching rate of the second underlying layer along a second axis perpendicular to the first axis.
11. The method of claim 10 , wherein the etching rate of the second underlying layer along the first axis is five to twenty times the etching rate of the second underlying layer along the second axis.
12. The method of claim 9 , wherein the first opening and the second opening are spaced apart from each other by an amount of S 1 , and the first groove and the second groove are spaced apart from each other by an amount of S 2 , where S 1 >S 2 .
13. The method of claim 12 , wherein the third opening and the fourth opening are spaced apart from each other by an amount of S 3 , where S 3 >S 2 .
14. The method of claim 13 , wherein S 3 >S 1 .
15. The method of claim 9 , wherein:
the first underlying layer is formed over a third layer disposed over the substrate,
a first conductive pattern and a second conductive pattern are formed in the third layer, and
the first opening is formed on the first conductive pattern and the second opening is formed on the second conductive pattern.
16. The method of claim 9 , wherein the first underlying layer and the second underlying layer are made of different dielectric materials from each other.
17. The method of claim 9 , wherein the resist pattern fills the first and second openings formed in the first underlying layer so that the third and fourth openings do not overlap the first and second openings formed in the first underlying layer, respectively.
18. The method of claim 10 , wherein a center line of the third opening along the first axis is not aligned, in the second axis, with a center line of the first groove along the first axis.
19. A method of manufacturing a semiconductor device, the method comprising:
forming a first underlying layer over a substrate and a second underlying layer over the first underlying layer;
forming a first resist pattern having a first opening and a second opening over the second underlying layer;
patterning the first and second underlying layers by using the first resist pattern as an etching mask, thereby forming a third opening and a fourth opening in the first and second underlying layers;
expanding the third opening and the fourth opening in a first axis by directional etching to form a first groove and a second groove in the second underlying layer;
forming a second resist pattern including a fifth opening only partially overlapping the first groove and a sixth opening only partially overlapping the second groove; and
patterning the second underlying layer by using the second resist pattern as an etching mask to form a first trench and a second trench in the second underlying layer, wherein the first opening and the second opening are spaced apart from each other by an amount of S 1 , and the first trench and the second trench are spaced apart from each other by an amount of S 2 , where S 1 >S 2 .
20. The method of claim 19 , wherein S 1 is equal to or greater than a minimum space patternable in a single lithography process used to form the first resist pattern.