IP Library › Granted Patent US 10,985,264
Granted Patent B2
US 10,985,264 · App. 16/378,584 · Granted Apr 20, 2021

Semiconductor device and method for fabricating the same

Inventors: Chin-Hung Chen (Tainan, TW); Ssu-I Fu (Kaohsiung, TW); Chih-Kai Hsu (Tainan, TW); Chia-Jung Hsu (Tainan, TW); Yu-Hsiang Lin (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/66795H01L21/0337H01L21/3086H01L27/0605H01L27/0886H01L29/7851H01L29/7856H01L27/1211
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Quick Facts
Patent No.
US 10,985,264
App. No.
16/378,584
Granted
Apr 20, 2021
Kind
B2
Abstract

A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Claims (15)

1. A semiconductor device, comprising:

a fin-shaped structure on a substrate, wherein the fin-shaped structure comprises:

a first semiconductor layer on the substrate;

a second semiconductor layer on the first semiconductor layer;

an insulating layer on the second semiconductor layer;

a third semiconductor layer on and directly contacting the insulating layer, wherein the first semiconductor layer and the third semiconductor layer comprise III-V semiconductors and a sidewall of the third semiconductor layer is aligned with a sidewall of the insulating layer; and

a shallow trench isolation (STI) around the first semiconductor layer, the second semiconductor layer, the insulating layer, and the third semiconductor layer, wherein a top surface of the third semiconductor layer is higher than a top surface of the STI.

2. The semiconductor device of claim 1 , further comprising a gate electrode on the STI and the fin-shaped structure.

3. The semiconductor device of claim 1 , wherein the second semiconductor layer comprises aluminum gallium nitride (AlGaN).

4. The semiconductor device of claim 1 , wherein the first semiconductor layer and the third semiconductor layer comprise a same material.

5. The semiconductor device of claim 4 , wherein the first semiconductor layer and the third semiconductor layer comprise gallium nitride (GaN).

6. The semiconductor device of claim 1 , wherein the first semiconductor layer and the substrate comprise a same material.

7. The semiconductor device of claim 6 , wherein the first semiconductor layer and the substrate comprise gallium nitride (GaN).

8. The semiconductor device of claim 1 , wherein the insulating layer comprises metal oxide.

9. The semiconductor device of claim 8 , wherein the insulating layer comprises aluminum oxide (Al 2 O 3 ).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2019
From: CHEN, CHIN-HUNG; FU, SSU-I; HSU, CHIH-KAI; HSU, CHIA-JUNG; LIN, YU-HSIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 048825/0001 →
Priority Claims (1)
CN 201910180883.1 · Mar 11, 2019 · national
Continuity (1)
Related Publication 20200295160A1 · Sep 17, 2020
Cited By (2)
US 12,266,696 US 12,389,624