Manufacturing method of semiconductor device
A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.
1. A manufacturing method of a semiconductor device, comprising:
forming a III-V compound barrier layer on a III-V compound semiconductor layer;
forming a gate trench in the III-V compound barrier layer;
forming a p-type doped III-V compound layer in the gate trench, wherein a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar;
forming an insulation layer on the III-V compound barrier layer before the step of forming the gate trench, wherein the III-V compound semiconductor layer, the III-V compound barrier layer, and the insulation layer are formed on a first region and a second region of a substrate;
forming an opening penetrating through the insulation layer in a vertical direction, wherein the opening is located corresponding to the gate trench in the vertical direction;
forming a first gate electrode on the p-type doped III-V compound layer and the insulation layer, wherein the opening, the gate trench, the p-type doped III-V compound layer, and the first gate electrode are formed on the first region of the substrate; and
forming a second gate electrode on the III-V compound barrier layer located on the second region of the substrate, wherein the first gate electrode and the second gate electrode are formed concurrently by the same process.
2. The manufacturing method of the semiconductor device according to claim 1 , wherein the opening and the gate trench are formed by a patterning process.
3. The manufacturing method of the semiconductor device according to claim 1 , further comprising:
forming a first source electrode and a first drain electrode on the III-V compound barrier layer located on the first region of the substrate, wherein the first source electrode and the first drain electrode are a source electrode and a drain electrode of a first transistor structure comprising the first gate electrode; and
forming a second source electrode and a second drain electrode on the III-V compound barrier layer located on the second region of the substrate, wherein the second source electrode and the second drain electrode are a source electrode and a drain electrode of a second transistor structure comprising the second gate electrode, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed concurrently by the same process.
4. The manufacturing method of the semiconductor device according to claim 3 , wherein the first transistor structure is an enhancement mode (E-mode) transistor, and the second transistor structure is a depletion mode (D-mode) transistor.
5. The manufacturing method of the semiconductor device according to claim 1 , wherein the p-type doped III-V compound layer is formed by a selective epitaxial growth process.
6. The manufacturing method of the semiconductor device according to claim 1 , wherein a distance between the top surface of the p-type doped III-V compound layer and a bottom surface of the III-V compound barrier layer in the vertical direction is equal to a thickness of the III-V compound barrier layer in the vertical direction with a tolerance of +10%.
7. The manufacturing method of the semiconductor device according to claim 1 , wherein a ratio of a thickness of the p-type doped III-V compound layer in the vertical direction to a thickness of the III-V compound barrier layer in the vertical direction is less than 1 and greater than or equal to 0.8.
8. The manufacturing method of the semiconductor device according to claim 1 , wherein the p-type doped III-V compound layer comprises a p-type doped aluminum gallium nitride layer, the III-V compound barrier layer comprises an aluminum gallium nitride layer, and an atomic concentration of aluminum in the p-type doped III-V compound layer is lower than an atomic concentration of aluminum in the III-V compound barrier layer.
9. The manufacturing method of the semiconductor device according to claim 1 , wherein the p-type doped III-V compound layer comprises a p-type doped Al x Ga 1-x N layer, and x is less than 1 and greater than or equal to 0.
10. The manufacturing method of the semiconductor device according to claim 1 , wherein a part of the III-V compound barrier layer is located between the gate trench and the III-V compound semiconductor layer in the vertical direction.