IP Library Granted Patent US 10,757,820
Granted Patent B2
US 10,757,820 · App. 16/382,079 · Granted Aug 25, 2020

Single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor

Inventors: Siping Bai (Zhuhai, CN); Xianglan Wu (Zhuhai, CN); Zhijian Wang (Zhuhai, CN); Zhigang Yang (Zhuhai, CN); Jinqiang Zhang (Zhuhai, CN)
Assignee: RICHVIEW ELECTRONICS CO., LTD.
H05K3/429C23C14/48H05K1/115H05K3/105H05K3/42H05K3/422H05K3/423H05K3/427H05K3/048H05K3/06H05K3/108H05K3/421H05K3/426H05K3/4617H05K2201/0355H05K2201/096H05K2203/0565H05K2203/0769H05K2203/092H05K2203/1423
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Quick Facts
Patent No.
US 10,757,820
App. No.
16/382,079
Granted
Aug 25, 2020
Kind
B2
Abstract

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board ( 10 ) comprises the following steps: drilling a hole on a substrate ( 11 ), the hole comprising a blind hole and/or a through hole (S 1 ); on a surface ( 12 ) of the substrate, forming a photoresist layer having a circuit negative image (S 2 ); forming a conductive seed layer on the surface ( 12 ) of the substrate and a hole wall ( 19 ) of the hole (S 3 ); removing the photoresist layer, and forming a circuit pattern on the surface ( 12 ) of the substrate (S 4 ), wherein Step S 3 comprises implanting a conductive material below the surface ( 12 ) of the substrate and below the hole wall ( 19 ) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Claims (3)

1. A single-layer circuit board, comprising substrate and circuit pattern layer formed on partial surface of said substrate, said substrate is provided with a hole, the hole comprises blind hole and/or through hole, the hole wall of said hole is formed with conductive seed layer, said circuit pattern layer comprises conductive seed layer formed to partial surface of said substrate, wherein said conductive seed layer comprises ion implantation layer implanted below partial surface of said substrate and below the hole wall of said hole.

2. The single-layer circuit board of claim 1 , wherein said ion implantation layer is located below partial surface of said substrate and below the hole wall of said hole for a depth of 1-500 nm, and forms steady doping structure with said substrate.

3. The single-layer circuit board of claim 1 , wherein said conductive seed layer further comprises plasma deposition layer adhered above said ion implantation layer, said plasma deposition layer has a thickness of 1-10000 nm.

Assignments (2)
CHANGE OF NAME Recorded Aug 6, 2025
From: RICHVIEW ELECTRONICS CO., LTD.
To: THINKTRANS ELECTRONIC MATERIALS (SHENZHEN) CO., LTD.
Reel/Frame 072361/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2020
From: BAI, SIPING; WU, XIANGLAN; WANG, ZHIJIAN; YANG, ZHIGANG; ZHANG, JINQIANG
To: RICHVIEW ELECTRONICS CO., LTD.
Reel/Frame 052260/0891 →
Priority Claims (1)
CN 2015 1 0747884 · Nov 6, 2015 · national
Continuity (2)
Division 15773772
Related Publication 20190306991A1 · Oct 3, 2019