Fabrication of embedded memory devices utilizing a self assembled monolayer

1. A semiconductor device structure comprising at least:

a metallization stack comprising one or more patterned metal layers in a memory area and a logic area;

a bi-layer dielectric cap disposed on and in direct contact with the metallization stack, the the bi-layer dielectric cap comprising a first dielectric layer and a second dielectric layer in the memory area, and comprising only the second dielectric layer in the logic area; and

at least one memory device comprising a magnetic tunnel junction stack, wherein a portion of with a bottom electrode in contact with the magnetic tunnel junction stack is disposed in direct contact with at least a portion of the bi-layer dielectric cap.

2. The semiconductor device structure of claim 1 , wherein the bottom electrode is disposed on and in contact with a bottom electrode contact, and wherein the bottom electrode contact is disposed on and in contact with one of the one or more patterned metal layers.

3. The semiconductor device structure of claim 2 , wherein a first dielectric layer of the bi-layer dielectric cap contacts the bottom electrode contact, and wherein a second dielectric layer of the bi-layer dielectric cap contacts the first dielectric layer.

4. The semiconductor device structure of claim 1 , further comprising:

an encapsulation layer disposed in contact with sidewalls of the memory device.

5. The semiconductor device structure of claim 4 , wherein the encapsulation layer is disposed on and contacts a top dielectric layer of the bi-layer dielectric cap.

6. The semiconductor device structure of claim 1 , wherein the memory device further comprises a top electrode disposed on and in contact with the magnetic tunnel junction stack.

7. The semiconductor device structure of claim 1 , wherein a top dielectric layer of the bi-layer dielectric cap comprises a lower dielectric constant than that of a bottom dielectric layer of the bi-layer dielectric cap.

8. A semiconductor device structure comprising at least:

a metallization stack comprising at least a first patterned metal layer in a memory area and at least a second patterned metal layer in a logic area;

a bi-layer dielectric cap disposed on and in direct contact with the metallization stack, wherein the bi-layer dielectric cap comprises a first dielectric layer and a second dielectric layer in the memory area, and comprises only the second dielectric layer in the logic area; and

at least one memory device disposed in direct contact with the bi-layer dielectric cap.

9. The semiconductor device structure of claim 8 , wherein a thickness of a top dielectric layer of the bi-layer dielectric cap is greater than a thickness of a bottom dielectric layer of the bi-layer dielectric cap in at least the logic area.

10. The semiconductor device structure of claim 8 , wherein a top dielectric layer of the bi-layer dielectric cap comprises a lower dielectric constant than that of a bottom dielectric layer of the bi-layer dielectric cap.

11. The semiconductor device structure of claim 8 , wherein a contact layer is disposed within the bi-layer dielectric cap and in contact with the first patterned metal layer, and wherein the memory device is disposed on and in contact with the contact layer.

12. A semiconductor device structure comprising at least:

a metallization stack comprising one or more patterned metal layers in a memory area and a logic area;

a bi-layer dielectric cap disposed on and in direct contact with the metallization stack, the bi-layer dielectric cap comprising a first dielectric layer and a second dielectric layer in the memory area, and comprising only the second dielectric layer in the logic area; and

at least one memory device disposed on the bi-layer dielectric cap, wherein a top surface of a portion of a first dielectric layer of the bi-layer dielectric cap and a top surface of a portion of a second dielectric layer of the bi-layer dielectric cap are co-planar.

13. The semiconductor device structure of claim 12 , wherein the memory device comprises a bottom electrode, a magnetic tunnel junction stack disposed on and in contact with the bottom electrode, and a top electrode disposed on and in contact with the magnetic tunnel junction stack.

14. The semiconductor device structure of claim 13 , wherein the bottom electrode is disposed on and in contact with a bottom electrode contact, and wherein the bottom electrode contact is disposed on and in contact with one of the one or more patterned metal layers.

15. The semiconductor device structure of claim 14 , wherein a first dielectric layer of the bi-layer dielectric cap contacts the bottom electrode contact, and wherein a second dielectric layer of the bi-layer dielectric cap contacts the first dielectric layer.

16. The semiconductor device structure of claim 12 , further comprising:

an encapsulation layer disposed in contact with sidewalls of the memory device.

17. The semiconductor device structure of claim 16 , wherein the encapsulation layer is disposed on and contacts a top dielectric layer of the bi-layer dielectric cap.

18. The semiconductor device structure of claim 12 , wherein a top dielectric layer of the bi-layer dielectric cap comprises a lower dielectric constant than that of a bottom dielectric layer of the bi-layer dielectric cap.

19. The semiconductor device structure of claim 12 , wherein a portion of the first dielectric layer is in direct contact with a spacer of a magnetic tunnel junction stack of the memory device and a portion of the second dielectric layer is in direct contact with a bottom electrode of the memory device.