Methods for fabricating semiconductor devices that have polycrystalline CVD diamond
A method of fabricating a semiconductor device structure includes: providing a substrate comprising a layer of compound semiconductor material; forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique. An effective thermal boundary resistance (TBR eff ) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m 2 K/GW.
1. A method of fabricating a semiconductor device structure, comprising:
providing a substrate comprising a layer of compound semiconductor material;
forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the layer of compound semiconductor material; and
growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique,
wherein an effective thermal boundary resistance (TBR eff ) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m 2 K/GW.
2. A method as recited in claim 1 , wherein the seed layer is formed using a nano-crystalline diamond powder having an average particle size of no more than 15 nm.
3. A method as recited in claim 2 , wherein the seed layer is formed using a nano-crystalline diamond powder having an average particle size of no less than 1 nm.
4. A method as recited in claim 1 , wherein a D90 particle size of nano-crystalline diamond powder used in the step of forming a seed layer is no more than 40 nm.
5. A method as recited in claim 1 , wherein the thickness of the seed layer is in a range 10 to 40 nm.
6. A method as recited in claim 1 , wherein the thickness of the seed layer is in a range 15 to 30 nm.
7. A method as recited in claim 1 , wherein the seed layer has a volume fraction of voids of no more than 10%.
8. A method as recited in claim 1 , wherein the seed layer has a volume fraction of voids of no more than 8%.
9. A method as recited in claim 1 , wherein the seed layer has no voids having a thickness greater than 20 nm in a representative sample comprising an area of at least 200 nm×100 nm.
10. A method as recited in claim 1 , wherein the layer of polycrystalline CVD diamond has a thickness of at least 5 micrometers.
11. A method as recited in claim 1 , wherein the layer of polycrystalline CVD diamond comprises grains having a size greater than 1 micron.
12. A method as recited in claim 1 , wherein the layer of compound semiconductor material comprises a III-V compound semiconductor material.
13. A method as recited in claim 12 , wherein the III-V compound semiconductor material is gallium nitride.
14. A method as recited in claim 1 , wherein the layer of compound semiconductor material has the following characteristics;
a charge mobility of at least 1200 cm 2 V −1 s −1 ;
a sheet resistance of no more than 700 Ω/square;
a current leakage of no more than 10 −5 amps; and
a maximum power of at least 5 W/mm.
15. A method for fabricating a semiconductor device structure, comprising:
providing a substrate comprising a layer of compound semiconductor material;
forming a dielectric layer on the substrate;
forming a seed layer of nano-crystalline diamond having a layer thickness in a range 5 to 50 nm on the dielectric layer; and
growing a layer of polycrystalline CVD diamond on the seed layer using a chemical vapour deposition (CVD) technique,
wherein the dielectric layer has a thickness in a range 28-100 nm and an effective thermal boundary resistance (TBR eff ) at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is 12-50 m 2 K/GW, and
wherein the seed layer has no voids having a thickness greater than 20 nm in a representative sample comprising an area of at least 200 nm×100 nm.
16. A method as recited in claim 15 , wherein the dielectric layer comprises a ceramic material.
17. A method as recited in claim 15 , wherein the layer of compound semiconductor material includes a GaN layer.
18. A method as recited in claim 16 , wherein the layer of compound semiconductor material includes an AlGaN layer and the GaN layer is disposed on the AlGaN layer.
19. A method as recited in claim 16 , wherein the seed layer has a volume fraction of voids of no more than 10%.
20. A method as recited in claim 15 , wherein the step of forming a seed layer includes using a colloidal suspension of nano-crystalline diamond powder with deposition parameters controlled to achieve the effective thermal boundary resistance (TBR eff ).