IP Library › Granted Patent US 10,998,262
Granted Patent B2
US 10,998,262 · App. 16/384,348 · Granted May 4, 2021

Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge

Inventors: Jiun Hann Sir (Gelugor, MY); Poh Boon Khoo (Perai, MY); Eng Huat Goh (Ayer Itam, MY); Amruthavalli Pallavi Alur (Tempe, AZ); Debendra Mallik (Chandler, AZ)
Assignee: Intel Corporation
H01L23/5226H01L24/09H01L24/17H01L2224/02371H01L2224/02372H01L2924/01029
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Quick Facts
Patent No.
US 10,998,262
App. No.
16/384,348
Granted
May 4, 2021
Kind
B2
Abstract

An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

Claims (57)

1. An integrated-circuit device package, comprising:

a first integrated-circuit die on an integrated-circuit package substrate, wherein the integrated-circuit package substrate includes a die side and a land side, the integrated-circuit package substrate comprising a plurality of layers including a penultimate layer and an ultimate layer, the ultimate layer on the penultimate layer, the ultimate layer comprising a single dielectric layer, and the ultimate layer distal from the land side of the integrated-circuit package substrate;

an interconnect bridge above the penultimate layer of the integrated-circuit package substrate;

the single dielectric layer over the interconnect bridge, wherein the single dielectric layer is penetrated by a bridge via that contacts the interconnect bridge, and wherein the single dielectric layer is penetrated by a package via that is electrically coupled to the land side of the integrated-circuit package substrate.

2. The integrated-circuit device package of claim 1 , wherein the interconnect bridge is on a die-attach film that is on the penultimate layer of the integrated-circuit package substrate.

3. The integrated-circuit device package of claim 1 , wherein the interconnect bridge is on a die-attach film that is on the penultimate layer of the integrated-circuit package substrate, and wherein the interconnect bridge has three conductive layers with a bottom conductive layer contacting the die-attach film, and a top conductive layer being contacted by the bridge via.

4. The integrated-circuit device package of claim 1 , wherein the interconnect bridge is on a die-attach film that is on the penultimate layer of the integrated-circuit package substrate, wherein the interconnect bridge has three conductive layers with a bottom conductive layer contacting the die-attach film, a top conductive layer being contacted by the bridge via, and wherein the interconnect bridge has a Z-height of about 10 micrometers.

5. The integrated-circuit device package of claim 1 , further including:

a first integrated-circuit die that is coupled to the bridge via that contacts the interconnect bridge, and that is coupled to the package via.

6. The integrated-circuit device package of claim 1 , further including:

a first integrated-circuit die that is coupled to the bridge via, wherein the bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the first integrated-circuit die; and

wherein the first integrated-circuit die is coupled to the land side through the package via, that contacts a copper pillar that contacts an electrical bump.

7. The integrated-circuit device package of claim 1 , further including:

a first integrated-circuit die that is coupled to the bridge via, wherein the bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the first integrated-circuit die;

wherein the first integrated-circuit die is coupled to the land side through the package via, that contacts a copper pillar that contacts an electrical bump;

a subsequent integrated-circuit die that is coupled to a subsequent bridge via, wherein the subsequent bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the subsequent integrated-circuit die; and

wherein the subsequent integrated-circuit die is coupled to the land side through a subsequent package via, that contacts a copper pillar that contacts an electrical bump.

8. The integrated-circuit device package of claim 1 , wherein the single dielectric layer is also over and contacting the penultimate layer.

9. The integrated-circuit device package of claim 8 , wherein the interconnect bridge is on a die-attach film that is on the penultimate layer of the integrated-circuit package substrate.

10. The integrated-circuit device package of claim 8 , wherein the interconnect bridge is on a die-attach film that is on the penultimate layer of the integrated-circuit package substrate, and wherein the interconnect bridge has three conductive layers with a bottom conductive layer contacting the die-attach film.

11. The integrated-circuit device package of claim 1 , further including: a first integrated-circuit die that is coupled to the bridge via that contacts the interconnect bridge, and that is coupled to the package via.

12. The integrated-circuit device package of claim 1 , further including:

a first integrated-circuit die that is coupled to the bridge via, wherein the bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the first integrated-circuit die; and

wherein the first integrated-circuit die is coupled to the land side through the package via, that contacts a copper pillar that contacts an electrical bump.

13. The integrated-circuit device package of claim 1 , wherein the ultimate layer contacts a release-layer inclusion, the interconnect bridge further including a polyimide film that is penetrated by the bridge via, and wherein the release-layer inclusion is between the polyimide film and the ultimate layer.

14. A computing system, comprising:

an integrated-circuit device package including a die side and a land side, the integrated-circuit package substrate comprising a plurality of layers including a penultimate layer and an ultimate layer, the ultimate layer on the penultimate layer, the ultimate layer comprising a single dielectric layer, and the ultimate layer distal from the land side of the integrated-circuit package substrate;

an interconnect bridge above the penultimate layer of the integrated-circuit package substrate;

the single dielectric layer covering over the interconnect bridge, wherein the single dielectric layer is penetrated by a bridge via that contacts the interconnect bridge, and wherein the single dielectric layer is penetrated by a package via that is electrically coupled to the land side of the integrated-circuit package substrate;

a first integrated-circuit die that is coupled to the bridge via, wherein the bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the first integrated-circuit die;

wherein the first integrated-circuit die is coupled to the land side through the package via, that contacts a copper pillar that contacts an electrical bump;

a subsequent integrated-circuit die that is coupled to a subsequent bridge via, wherein the subsequent bridge via contacts a copper bridge pad, that contacts an electrical bump, that contacts the subsequent integrated-circuit die;

wherein the subsequent integrated-circuit die is coupled to the land side through a subsequent package via, that contacts a copper pillar that contacts an electrical bump; and

wherein the first and subsequent integrated-circuit dice are part of a chipset.

15. The computing system of claim 14 , further including more than one chiplet on the first integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the first integrated-circuit die through a through-silicon via.

16. The computing system of claim 14 , further including:

more than one chiplet on the first integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the first integrated-circuit die through a through-silicon via; and

more than one chiplet on the subsequent integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the subsequent integrated-circuit die through a through-silicon via.

17. The computing system of claim 14 , further including:

more than one chiplet on the first integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the first integrated-circuit die through a through-silicon via;

more than one chiplet on the subsequent integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the subsequent integrated-circuit die through a through-silicon via; and

wherein at least one of the more than one chiplets on the first integrated-circuit, at least one of the more than one chiplets on the subsequent integrated-circuit die, and at least one of the first and subsequent integrated-circuit dice comprise a disaggregated logic processor.

18. The computing system of claim 14 , further including:

more than one chiplet on the first integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the first integrated-circuit die through a through-silicon via;

more than one chiplet on the subsequent integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the subsequent integrated-circuit die through a through-silicon via; and

wherein at least one of the more than one chiplets on the first integrated-circuit comprises a disaggregated graphics processor, wherein at least one of the more than one chiplets on the subsequent integrated-circuit die comprises a disaggregated graphics processor, and at least one of the first and subsequent integrated-circuit dice comprises a disaggregated graphics processor.

19. The computing system of claim 14 , further including:

more than one chiplet on the first integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the first integrated-circuit die through a through-silicon via;

more than one chiplet on the subsequent integrated-circuit die at a backside, wherein one of the more than one chiplets communicates to the subsequent integrated-circuit die through a through-silicon via;

wherein at least one of the more than one chiplets on the first integrated-circuit, wherein at least one of the more than one chiplets on the subsequent integrated-circuit die, and at least one of the first and subsequent integrated-circuit dice comprise a disaggregated logic processor, and wherein at least one of the more than one chiplets on the first integrated-circuit, wherein at least one of the more than one chiplets on the subsequent integrated-circuit die, and at least one of the first and subsequent integrated-circuit dice comprise a disaggregated graphics processor.

20. A process of forming an interconnect bridge, comprising:

patterning a metallization on an inorganic substrate, including patterning three metallization layers including vias and traces;

stripping the inorganic substrate after seating the metallization on a die-attach film of an integrated-circuit package substrate; and

forming a single dielectric layer over the metallization and the integrated-circuit package substrate.

21. The process of claim 20 , wherein patterning includes patterning with a top layer first and a bottom layer last, followed by inverting the metallization when seating the metallization on the die-attach film.

22. The process of claim 20 , further including connecting a first and a subsequent integrated-circuit die to the metallization through the single dielectric layer.

23. The process of claim 20 , wherein patterning the metallization on the inorganic substrate includes transmitting light energy through the inorganic substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2020
From: SIR, JIUN HANN; KHOO, POH BOON; GOH, ENG HUAT; ALUR, AMRUTHAVALLI PALLAVI; MALLIK, DEBENDRA
To: INTEL CORPORATION
Reel/Frame 051490/0561 →
Continuity (1)
Related Publication 20200328151A1 · Oct 15, 2020