Semiconductor device

1. A semiconductor device comprising:

a substrate comprising a first region and a second region;

a buried gate structure located on a first recess in the first region of the substrate and comprising a first work function adjustment layer; and

a recess gate structure located on a second recess in the second region of the substrate and comprising a second work function adjustment layer,

wherein the buried gate structure is buried in the substrate,

wherein an upper portion of the recess gate structure is not buried in the substrate,

wherein the first work function adjustment layer in the buried gate structure and the second work function adjustment layer in the recess gate structure comprise the same material, and

wherein a depth of the first recess is greater than a depth of the second recess.

2. The semiconductor device of claim 1 ,

wherein each of the first work function adjustment layer in the buried gate structure and the second work function adjustment layer in the recess gate structure comprises a metal-metal nitride alloy.

3. The semiconductor device of claim 2 ,

wherein each of the first work function adjustment layer in the buried gate structure and the second work function adjustment layer in the recess gate structure comprises lanthanum-titanium nitride alloy.

4. The semiconductor device of claim 1 , further comprising:

a bit line contact, an interface layer, a bit line, and a bit line capping layer sequentially stacked in the first region of the substrate,

wherein the upper portion of the recess gate structure comprises a first gate layer, a second gate layer, a third gate layer, and a gate capping layer which are sequentially stacked, and

wherein each of the bit line contact, the interface layer, the bit line, and the bit line capping layer comprises a material the same as a material included in each of the first gate layer, the second gate layer, the third gate layer, and the gate capping layer, respectively.

5. The semiconductor device of claim 1 ,

wherein the buried gate structure further comprises a lower filling layer at a lower portion of the buried gate structure, and a barrier layer between the first recess and the lower filling layer.

6. The semiconductor device of claim 1 ,

wherein the buried gate structure further comprises an upper filling layer at an upper portion of the buried gate structure, and

wherein the first work function adjustment layer is located between the first recess and the upper filling layer.

7. The semiconductor device of claim 1 ,

wherein the buried gate structure is a portion of a first N-type transistor, and

the recess gate structure is a portion of a second N-type transistor.

8. A semiconductor device comprising:

a substrate comprising a first region and a second region;

a buried gate structure on a first recess in the first region of the substrate; and

a recess gate structure on a second recess in the second region of the substrate,

wherein the buried gate structure comprises a first gate insulating layer on the first recess, a lower filling layer at a lower portion of the buried gate structure, an upper filling layer at an upper portion of the buried gate structure, and a first work function adjustment layer between the upper filling layer and the first gate insulating layer,

wherein the recess gate structure comprises a second gate insulating layer on the second recess, a second work function adjustment layer on the second gate insulating layer, and a filling layer on the second work function adjustment layer,

wherein the first work function adjustment layer comprises a material the same as a material included in the second work function adjustment layer,

wherein the first work function adjustment layer comprises a portion between the lower filling layer and the upper filling layer,

wherein the recess gate structure further comprises a first gate layer, a second gate layer, a third gate layer, and a gate capping layer sequentially stacked on the filling layer, and

wherein the first gate layer, the second gate layer, the third gate layer, and the gate capping layer are not buried in the substrate.

9. The semiconductor device of claim 8 ,

wherein the buried gate structure further comprises a barrier layer between the lower filling layer and the first gate insulating layer.

10. The semiconductor device of claim 8 ,

wherein a portion of each of the second gate insulating layer, the second work function adjustment layer, and the filling layer is buried in the substrate.

11. The semiconductor device of claim 8 , further comprising:

a bit line contact, an interface layer, a bit line, and a bit line capping layer sequentially stacked on the first region of the substrate,

wherein each of the bit line contact, the interface layer, the bit line, and the bit line capping layer comprises a material the same as a material included in each of the first gate layer, the second gate layer, the third gate layer, and the gate capping layer in the recess gate structure, respectively.

12. A semiconductor device comprising:

a substrate comprising a first region, a second region, and a third region;

a buried gate structure comprising a first gate insulating layer on a first recess in the first region of the substrate and a first work function adjustment layer on the first gate insulating layer;

a first recess gate structure comprising a second gate insulating layer on a second recess in the second region of the substrate and a second work function adjustment layer on the second gate insulating layer; and

a second recess gate structure comprising a third gate insulating layer on a third recess in the third region of the substrate and a third work function adjustment layer on the third gate insulating layer,

wherein the first work function adjustment layer and the second work function adjustment layer comprise a same material,

wherein the first work function adjustment layer and the third work function adjustment layer comprise different materials,

wherein the buried gate structure is a portion of a first N-type transistor,

wherein the first recess gate structure is a portion of a second N-type transistor, and

wherein the second recess gate structure is a portion of a P-type transistor.

13. The semiconductor device of claim 12 ,

wherein the third work function adjustment layer comprises a metal-metal nitride alloy.

14. The semiconductor device of claim 13 ,

wherein the third work function adjustment layer comprises aluminum-titanium nitride alloy.

15. The semiconductor device of claim 12 ,

wherein the second recess gate structure further comprises a fourth work function adjustment layer on the third work function adjustment layer.

16. The semiconductor device of claim 15 ,

wherein the fourth work function adjustment layer comprises a material the same as a material included in the first work function adjustment layer.