Self-limiting and confining epitaxial nucleation
A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
1. A semiconductor device comprising:
a fin patterned in a substrate, the fin comprising a spacer arranged on a sidewall of the fin;
isolation regions arranged on the substrate and around the fin, the spacer contacting one of the isolation regions;
a spacer material arranged over the fin, a portion of the fin lining a lateral sidewall of the spacer material;
a tapered recess arranged within the fin; and
a semiconductor material arranged within the tapered recess.
2. The semiconductor device of claim 1 , wherein the spacer material comprises a dielectric material.
3. The semiconductor device of claim 1 , wherein the spacer comprises a low-k material.
4. The semiconductor device of claim 1 , wherein the spacer material comprises SiBN, SiCN, SiBCN, or any combination thereof.
5. The semiconductor device of claim 1 , wherein the semiconductor material comprises an epitaxial growth material.
6. The semiconductor device of claim 1 , wherein the fin comprises a nanosheet stack.
7. The semiconductor device of claim 1 , wherein the semiconductor device is a nanosheet FET.
8. The semiconductor device of claim 1 , wherein the semiconductor device is a FinFET.
9. The semiconductor device of claim 1 further comprising a metal disposed on the spacer and the semiconductor material to form a source/drain contact.
10. The semiconductor device of claim 1 , wherein the recess comprises a tapered opening.
11. A semiconductor device comprising:
a fin patterned in a substrate, the fin comprising a spacer arranged on a sidewall of the fin;
isolation regions arranged on the substrate and around the fin, the spacer contacting one of the isolation regions;
a spacer material arranged over the fin, a portion of the fin lining a lateral sidewall of the spacer material;
a v-shaped recess arranged within the fin; and
a semiconductor material arranged within the v-shaped recess.
12. The semiconductor device of claim 11 , wherein the spacer material comprises a dielectric material.
13. The semiconductor device of claim 11 , wherein the spacer comprises a low-k material.
14. The semiconductor device of claim 11 , wherein the spacer material comprises SiBN, SiCN, SiBCN, or any combination thereof.
15. The semiconductor device of claim 11 , wherein the semiconductor material comprises an epitaxial growth material.
16. The semiconductor device of claim 11 , wherein the fin comprises a nanosheet stack.
17. The semiconductor device of claim 11 , wherein the semiconductor device is a nanosheet FET.
18. The semiconductor device of claim 11 , wherein the semiconductor device is a FinFET.
19. The semiconductor device of claim 11 further comprising a metal disposed on the spacer and the semiconductor material to form a source/drain contact.
20. The semiconductor device of claim 1 , wherein the fin comprises another semiconductor material.