IP Library Granted Patent US 11,099,597
Granted Patent B2
US 11,099,597 · App. 16/389,340 · Granted Aug 24, 2021

Interface system

Inventors: Toshitada Saito (Yokohama, JP); Akihisa Fujimoto (Yamato, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G06F1/06G06F1/12G06F13/38G06F13/4282H03L7/00H03L7/07H03L7/0807H03L7/091H03L7/099H04L7/0004H04L7/033H04L25/085H04L25/14H04L7/0012
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Quick Facts
Patent No.
US 11,099,597
App. No.
16/389,340
Granted
Aug 24, 2021
Kind
B2
Abstract

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Claims (27)

1. An interface system connectable to a host, the system comprising:

a receiver configured to receive a first clock and serial data from the host;

a first clock generator including a first voltage controlled oscillator (VCO) and configured to generate a second clock on the basis of the first clock;

a second clock generator including a second voltage controlled oscillator (VCO) and configured to generate a third clock on the basis of the serial data;

a sampling circuit configured to sample reception data on the basis of the third clock and the serial data; and

a controller configured to control a first state where the first and second clock generators are in an operating state and a second state where the first and second clock generators are in a non-operating state, wherein

the first clock and the serial data are supplied to the receiver in the first state and are not supplied to the receiver in the second state, and

the controller is further configured to, in a first recovery mode, start sampling of the reception data or transmitting of transmission data to the host after a certain period of time after confirming a transition from the second state to the first state, and not transmit a response indicative of establishment of synchronization of the second and third clocks to the host.

2. The interface system of claim 1 , wherein

the controller is further configured to transfer the response indicative of establishment of synchronization of the second and third clocks to the host and then start sampling of the reception data or transmitting of the transmission data to the host, when confirming a transition from the second state to the first state in a second recovery mode.

3. The interface system of claim 2 , wherein

the controller is further configured to:

control a third state where the first clock generator is in an operating state and the second clock generator is in a non-operating state, and

in a third recovery mode, start sampling of the reception data or transmitting of transmission data to the host after a certain period of time after confirming a transition from the third state to the first state, and not transmit a response indicative of establishment of synchronization of the second and third clocks to the host.

4. The interface system of claim 3 , wherein

the controller is further configured to confirm a transition from the second state to the first state, or a transition from the third state to the first state, on the basis of a command from the host.

5. The interface system of claim 4 , wherein the command includes a flag which selects one of the first, second, and third recovery modes.

6. The interface system of claim 5 , wherein the controller is further configured to set the first and second clock generators to the first state in a normal operation mode, and set the first and second clock generators to the second or third state in a power saving mode, and

power consumption of the second state is less than power consumption of the third state.

7. The interface system of claim 1 , wherein frequency of the second clock and frequency of the third clocks are locked in the certain period of time.

8. The interface system of claim 1 , wherein the first clock generator includes a memory unit configured to store an initial control voltage of the first voltage controlled oscillator (VCO).

9. The interface system of claim 8 , wherein the memory unit stores a control voltage of the first voltage controlled oscillator (VCO) as the initial control voltage when the frequency of the second clock is locked in the first state before the first recovery mode, and applies the initial control voltage to the first voltage controlled oscillator (VCO) in the first recovery mode.

10. The interface system of claim 9 , wherein a data transmission rate of the reception data or the transmission data in the first state before the first recovery mode is substantially the same as a data transmission rate of the reception data or the transmission data in the first state after the first recovery mode.

11. The interface system of claim 1 , wherein

the controller is further configured to confirm a transition from the second state to the first state, on the basis of a command from the host.

12. The interface system of claim 2 , wherein

the controller is further configured to confirm a transition from the second state to the first state, on the basis of a command from the host.

Assignments (2)
CHANGE OF NAME Recorded Aug 30, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 057352/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2019
From: SAITO, TOSHITADA; FUJIMOTO, AKIHISA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 049332/0186 →
Priority Claims (1)
JP JP2016-206337 · Oct 20, 2016 · national
Continuity (2)
Continuation PCTIB2017055411 · Sep 8, 2017
Related Publication 20190243410A1 · Aug 8, 2019
Cited By (1)
US 12,228,960