IP Library Granted Patent US 12,228,960
Granted Patent B2
US 12,228,960 · App. 18/601,440 · Granted Feb 18, 2025

Interface system

Inventors: Toshitada Saito (Yokohama, JP); Akihisa Fujimoto (Yamato, JP)
Assignee: KIOXIA CORPORATION
G06F1/06G06F1/12G06F13/38G06F13/4282H03L7/00H03L7/07H03L7/0807H03L7/091H03L7/099H04L7/0004H04L7/033H04L25/085H04L25/14H04L7/0012
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Quick Facts
Patent No.
US 12,228,960
App. No.
18/601,440
Granted
Feb 18, 2025
Kind
B2
Abstract

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Claims (34)

1. A method of controlling a memory card connectable to a host, the memory card comprising a host interface and a controller, the host interface including a receiver and a first clock generator, the receiver being configured to receive a first clock and serial data from the host, the method comprising:

generating a second clock on the basis of the first clock by the first clock generator;

managing states of the memory card, the states including an active state and a first dormant state;

supplying the first clock and the serial data to the receiver in the active state and not supplying the first clock and the serial data to the receiver in the first dormant state, wherein the first clock generator is in an operating state in the active state and the first clock generator is in a non-operating state in the first dormant state; and

in a first recovery mode, starting reception of data from the host or transmission of data to the host after confirming a transition from the first dormant state to the active state, without performing a handshake check.

2. The method of claim 1 , wherein

the host interface further includes a second clock generator and a sampling circuit,

the second clock generator is in an operating state in the active state and the second clock generator is in a non-operating state in the first dormant state, and

the method further comprises:

generating a third clock on the basis of the serial data by the second clock generator;

sampling reception data on the basis of the third clock and the serial data by the sampling circuit; and

in the first recovery mode, starting the sampling of the reception data or the transmission of data to the host after confirming the transition from the first dormant state to the active state, without performing the handshake check.

3. The method of claim 2 , wherein

frequency of the second clock and frequency of the third clock are locked in a first period of time,

the starting includes starting the sampling of the reception data or the transmission of data to the host after the first period of time after confirming the transition from the first dormant state to the active state.

4. The method of claim 3 , further comprising:

in a second recovery mode, transmitting a response indicative of establishment of synchronization of the second and third clocks to the host through the host interface after confirming the transition from the first dormant state to the active state, and then starting the sampling of the reception data or the transmission of data to the host.

5. The method of claim 4 , further comprising:

managing the active state, the first dormant state, and a second dormant state as the states of the memory card, wherein the first clock generator is in an operating state in the second dormant state and the second clock generator is in a non-operating state in the second dormant state; and

in a third recovery mode, starting the sampling of the reception data or the transmission of data to the host after confirming a transition from the second dormant state to the active state, and not transmitting the response indicative of establishment of synchronization of the second and third clocks to the host.

6. The method of claim 5 , further comprising:

confirming a transition from the first dormant state to the active state or a transition from the second dormant state to the active state, on the basis of a command from the host.

7. The method of claim 6 , wherein the command includes a flag that specifies one of the first, second, and third recovery modes.

8. The memory card of claim 7 , further comprising:

setting the first and second clock generators to the active state in a normal operation mode, and setting the first and second clock generators to the first dormant state or the second dormant state in a power saving mode, wherein

power consumption of the first dormant state is less than power consumption of the second dormant state.

9. The memory card of claim 4 , further comprising:

confirming a transition from the first dormant state to the active state, on the basis of a command from the host.

10. The method of claim 1 , wherein the first clock generator includes a first voltage controlled oscillator (VCO) and a memory unit configured to store an initial control voltage of the first voltage controlled oscillator (VCO).

11. The method of claim 10 , further comprising:

saving a control voltage of the first voltage controlled oscillator (VCO) into the memory unit as the initial control voltage when frequency of the second clock is locked in the active state, and applying the saved control voltage to the first voltage controlled oscillator (VCO) as the initial control voltage in the first recovery mode.

12. The method of claim 11 , wherein a data transmission rate between the host and the memory card in the active state before the first recovery mode is substantially the same as a data transmission rate between the host and the memory card in the active state after the first recovery mode.

13. The method of claim 1 , further comprising:

confirming a transition from the first dormant state to the active state, on the basis of a command from the host.

Priority Claims (1)
JP 2016-206337 · Oct 20, 2016 · national
Continuity (6)
Continuation 18301669 · Apr 17, 2023
Continuation 17885925 · Aug 11, 2022
Continuation 17375054 · Jul 14, 2021
Continuation 16389340 · Apr 19, 2019
Continuation PCTIB2017055411 · Sep 8, 2017
Related Publication 20240219952A1 · Jul 4, 2024
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