Power MOSFETs and methods for manufacturing the same
A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
1. A semiconductor device, comprising:
a substrate;
a field plate over the substrate;
a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate;
a first dielectric between the first portion of the gate electrode and the field plate; and
wherein the field plate is overlapping with a boundary of a first drift region and a second drift region in the substrate.
2. The semiconductor device of claim 1 , further comprising a second spacer laterally surrounding the gate electrode.
3. The semiconductor device of claim 2 , wherein the second spacer further laterally surrounding the first spacer.
4. The semiconductor device of claim 1 , further comprising a first spacer laterally surrounding the first dielectric.
5. The semiconductor device of claim 4 , further comprising a second dielectric underlying the first dielectric and the first spacer.
6. The semiconductor device of claim 5 , further comprising a third dielectric laterally abutting the second dielectric.
7. The semiconductor device of claim 6 , wherein the second portion of the gate electrode is directly over the third dielectric.
8. A semiconductor device, comprising:
a substrate having a top surface;
a field plate over the substrate;
a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate; and
a first dielectric between the substrate and the field plate;
an inner spacer on the top surface of the first dielectric; and
an outer spacer on the substrate and in contact with a sidewall of the first dielectric,
wherein the field plate is overlapping with a boundary of a first drift region and a second drift region in the substrate.
9. The semiconductor device of claim 8 , wherein the inner spacer isolates the field plate and the gate electrode.
10. The semiconductor device of claim 8 , wherein the outer spacer is further in contact with a sidewall of the gate electrode.
11. The semiconductor device of claim 8 , wherein the gate electrode and the field plate are between a source region and a drain region in the substrate.
12. The semiconductor device of claim 8 , further comprising a silicide layer covering the first portion and the second portion of the gate electrode.
13. The semiconductor device of claim 8 , further comprising a second dielectric between the field plate and the first portion of the gate electrode.
14. The semiconductor device of claim 13 , further comprising a third dielectric between the second portion of the gate electrode and the top surface of the substrate.
15. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a first drift region and a second drift region in the substrate;
forming a field plate over the substrate, the field plate overlapping with a boundary of the first drift region and the second drift region;
forming an inner spacer surrounding a sidewall of the field plate;
forming a conductive layer over the inner spacer; and
forming an outer spacer on the substrate and in contact with a sidewall of the inner spacer.
16. The method of claim 15 , further comprising forming a gate dielectric prior to forming the conductive layer.
17. The method of claim 15 , wherein forming the conductive layer further comprising conformally forming the conductive layer over the field plate and a top surface of the substrate.
18. The method of claim 15 , further comprising forming a first dielectric over the field plate prior to forming the inner spacer.
19. The method of claim 18 , further comprising patterning the conductive layer to form a gate electrode covering a portion of the top surface of the substrate, the sidewall of the inner spacer, and a portion of a top surface of the first dielectric.
20. The method of claim 19 , wherein forming the outer spacer is performed subsequent to patterning the conductive layer.