Transistor comprising an oxide semiconductor
An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
1. A transistor comprising:
a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a region overlapping with the gate electrode layer with the gate insulating layer provided therebetween;
a first insulating layer over the oxide semiconductor layer;
a second insulating layer over the first insulating layer; and
a source electrode layer and a drain electrode layer,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein a side surface of the oxide semiconductor layer is in contact with a side surface of the source electrode layer or a side surface of the drain electrode layer,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer,
wherein the oxide semiconductor layer comprises a crystal region including a nanocrystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm,
wherein an end portion of the oxide semiconductor layer has a tapered shape, and
wherein c-axes of crystal grains in the crystal region are oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
2. The transistor according to claim 1 , wherein the gate electrode layer contains a metal material selected from Al, Cr, Ta, Ti, Mo, and W.
3. The transistor according to claim 1 , wherein the source electrode layer and the drain electrode layer contain a metal material selected from Al, Cu, Cr, Ta, Ti, Mo, and W.
4. The transistor according to claim 1 , wherein the oxide semiconductor layer has a thickness greater than or equal to 5 nm and less than or equal to 200 nm.
5. The transistor according to claim 1 ,
wherein the gate electrode layer is provided under the oxide semiconductor layer with the gate insulating layer provided therebetween, and
wherein the gate insulating layer contains silicon oxide.
6. The transistor according to claim 1 ,
wherein the gate electrode layer is provided over the oxide semiconductor layer with the gate insulating layer provided therebetween, and
wherein the gate insulating layer contains silicon oxide.
7. The transistor according to claim 1 ,
wherein the gate electrode layer is configured to be a first gate electrode layer,
wherein the gate insulating layer is configured to be a first gate insulating layer,
wherein the transistor further comprises a second gate electrode layer and a second gate insulating layer, and
wherein the first gate electrode layer comprises a region overlapping with the second gate electrode layer with the oxide semiconductor layer provided therebetween.
8. The transistor according to claim 7 , wherein the first gate insulating layer and the second gate insulating layer comprise silicon oxide.
9. The transistor according to claim 1 , wherein the nanocrystal is present in a superficial portion of the oxide semiconductor layer.
10. A transistor comprising:
a gate electrode layer;
a gate insulating layer;
an oxide semiconductor layer comprising a first region overlapping with the gate electrode layer with the gate insulating layer provided therebetween and a second region whose resistance is lower than the resistance of the first region;
a first insulating layer over the oxide semiconductor layer;
a second insulating layer over the first insulating layer; and
a source electrode layer and a drain electrode layer,
wherein the oxide semiconductor layer comprises indium, gallium, and zinc,
wherein a side surface of the oxide semiconductor layer is in contact with a side surface of the source electrode layer or a side surface of the drain electrode layer,
wherein the source electrode layer and the drain electrode layer overlap with the gate electrode layer,
wherein the oxide semiconductor layer comprises a crystal region including a nanocrystal with a particle size greater than or equal to 1 nm and less than or equal to 20 nm,
wherein an end portion of the oxide semiconductor layer has a tapered shape, and
wherein c-axes of crystal grains in the crystal region are oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.
11. The transistor according to claim 10 , wherein the gate electrode layer contains a metal material selected from Al, Cr, Ta, Ti, Mo, and W.
12. The transistor according to claim 10 , wherein the source electrode layer and the drain electrode layer contain a metal material selected from Al, Cu, Cr, Ta, Ti, Mo, and W.
13. The transistor according to claim 10 , wherein the oxide semiconductor layer has a thickness greater than or equal to 5 nm and less than or equal to 200 nm.
14. The transistor according to claim 10 ,
wherein the gate electrode layer is provided under the oxide semiconductor layer with the gate insulating layer provided therebetween, and
wherein the gate insulating layer contains silicon oxide.
15. The transistor according to claim 10 ,
wherein the gate electrode layer is provided over the oxide semiconductor layer with the gate insulating layer provided therebetween, and
wherein the gate insulating layer contains silicon oxide.
16. The transistor according to claim 10 ,
wherein the gate electrode layer is configured to be a first gate electrode layer,
wherein the gate insulating layer is configured to be a first gate insulating layer,
wherein the transistor further comprises a second gate electrode layer and a second gate insulating layer, and
wherein the first gate electrode layer comprises a region overlapping with the second gate electrode layer with the oxide semiconductor layer provided therebetween.
17. The transistor according to claim 16 , wherein the first gate insulating layer and the second gate insulating layer comprise silicon oxide.
18. The transistor according to claim 10 , wherein the nanocrystal is present in a superficial portion of the oxide semiconductor layer.