Asynchronous successive approximation analog-to-digital converter and related methods and apparatus
An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.
1. An apparatus, comprising:
at least one ultrasonic transducer;
a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADCs) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR ADC in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry,
wherein a DAC update event of the at least one SAR ADC following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other SAR ADC in the plurality of SAR ADCs, and
wherein conversion of a next bit of the at least one SAR ADC after the at least one bit conversion is triggered by the DAC update event.
2. The apparatus of claim 1 , wherein the at least one ultrasonic transducer comprises an M×N array of ultrasonic transducers.
3. The apparatus of claim 1 , wherein the DAC update event is not synchronized to a system clock of the apparatus.
4. The apparatus of claim 1 , wherein conversion of a most significant bit (MSB) of the at least one SAR ADC is synchronized to a system clock or a sampling clock of the apparatus.
5. The apparatus of claim 4 , wherein conversion of bits of the at least one SAR ADC other than the MSB are not synchronized to the system clock of the apparatus.
6. The apparatus of claim 4 , wherein conversion of at least two bits, but not all bits, of the SAR ADC is synchronized to the system clock or the sampling clock of the apparatus.
7. The apparatus of claim 1 , wherein conversion of more than one bit, but not all bits of the at least one SAR ADC, is synchronous.
8. A method of operating an ultrasound device having a plurality of ultrasonic transducers and a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADCs), each ultrasonic transducer being respectively coupled to a SAR ADC, each asynchronous SAR ADC in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, the method comprising:
converting, in response to a first clock signal, a first bit of one SAR ADC in the plurality of SAR ADCs;
updating a DAC in the one SAR ADC in response to the converting; and
updating a DAC in another SAR ADC in the plurality of SAR ADCs in response to the updating a DAC in the one SAR ADC.
9. The method of claim 8 , wherein the first clock signal is a system clock.
10. The method of claim 8 , wherein a clock rate of the first clock signal is approximately a sampling frequency.
11. The method of claim 8 , further comprising converting additional bits of the one SAR ADC in addition to the first bit of the one SAR ADC in response to the updating the DAC.
12. The method of claim 8 , wherein conversion of at least two bits, but not all bits, of the one SAR ADC is synchronized to the first clock signal.