Self-aligned gate edge and local interconnect
Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
1. An integrated circuit structure, comprising:
a first semiconductor fin disposed above a substrate and having a length in a first direction;
a first gate structure disposed over the first semiconductor fin, the first gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction;
first and second gate edge isolation structures, wherein the first gate edge isolation structure is spaced equally from a first side of the first semiconductor fin as the second gate edge isolation structure is spaced from a second side of the first semiconductor fin;
second and third semiconductor fins disposed above the substrate without an intervening gate edge isolation structure between the second and third semiconductor fins, the second and third semiconductor fins having a length in the first direction, wherein the second gate edge isolation structure is spaced equally from the second side of the first semiconductor fin and a side of the second semiconductor fin proximate the second gate edge isolation structure;
a second gate structure disposed over the second and third semiconductor fins, the second gate structure having a first end opposite a second end in the second direction; and
a third gate edge isolation structure spaced equally from a side of the third semiconductor fin proximate the third gate edge isolation structure as the second gate edge isolation structure is spaced from the side of the second semiconductor fin proximate the second gate edge isolation structure.
2. The integrated circuit structure of claim 1 , wherein the first gate edge isolation structures is disposed directly adjacent to the first end of the first gate structure, and the second gate edge isolation structure is disposed directly adjacent to the second end of the first gate structure.
3. The integrated circuit structure of claim 2 , wherein the second gate edge isolation structure is disposed directly adjacent to the first end of the second gate structure, and the third gate edge isolation structure is disposed directly adjacent to the second end of the second gate structure.
4. The integrated circuit structure of claim 1 , wherein the first and second gate structures comprise a high-k gate dielectric layer and a metal gate electrode.
5. The integrated circuit structure of claim 1 , further comprising:
source or drain regions disposed in the first, second and third semiconductor fins.
6. The integrated circuit structure of claim 1 , further comprising:
a local interconnect disposed above and electrically coupling the first and second gate structures.
7. The integrated circuit structure of claim 6 , wherein the local interconnect is self-aligned with the first, second and third gate edge isolation structures.
8. The integrated circuit structure of claim 1 , wherein the first gate structure is an N-type gate structure, and the second gate structure is a P-type gate structure.
9. The integrated circuit structure of claim 1 , wherein the first gate structure is a P-type gate structure, and the second gate structure is an N-type gate structure.
10. The integrated circuit structure of claim 1 , wherein the first gate structure is an N-type gate structure, and the second gate structure is an N-type gate structure.
11. The integrated circuit structure of claim 1 , wherein the first gate structure is a P-type gate structure, and the second gate structure is a P-type gate structure.
12. The integrated circuit structure of claim 1 , wherein the first, second and third gate edge isolation structures comprise a material selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, and a combination thereof.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first semiconductor fin disposed above a substrate and having a length in a first direction;
a first gate structure disposed over the first semiconductor fin, the first gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction;
first and second gate edge isolation structures, wherein the first gate edge isolation structure is spaced equally from a first side of the first semiconductor fin as the second gate edge isolation structure is spaced from a second side of the first semiconductor fin;
second and third semiconductor fins disposed above the substrate without an intervening gate edge isolation structure between the second and third semiconductor fins, the second and third semiconductor fins having a length in the first direction, wherein the second gate edge isolation structure is spaced equally from the second side of the first semiconductor fin and a side of the second semiconductor fin proximate the second gate edge isolation structure;
a second gate structure disposed over the second and third semiconductor fins, the second gate structure having a first end opposite a second end in the second direction; and
a third gate edge isolation structure spaced equally from a side of the third semiconductor fin proximate the third gate edge isolation structure as the second gate edge isolation structure is spaced from the side of the second semiconductor fin proximate the second gate edge isolation structure.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , further comprising:
a camera coupled to the board.
17. The computing device of claim 13 , further comprising:
a battery coupled to the board.
18. The computing device of claim 13 , further comprising:
an antenna coupled to the board.
19. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 13 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.