Diode connected vertical transistor
An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.
1. A method of forming an electrical device comprising:
forming a transistor device in a first region of a substrate comprising a transistor channel, a first transistor source/drain region that is provided by an electrically conductive region at a first end of the transistor channel, and a transistor gate structure that is separated from the first transistor source/drain region of the transistor by a dielectric spacer; and
forming a diode connected transistor device in a second region of the substrate comprising a diode channel, a first diode source/drain region provided by the electrically conductive region at a first end of the diode channel, and a diode gate structure in direct contact with the first diode source/drain region.
2. The method of claim 1 , further comprising forming a second transistor source/drain region that is present at a second end of the transistor channel that is opposing the first end that is in contact with the first transistor source/drain region.
3. The method of claim 1 , further comprising forming a second diode transistor source/drain region that is present at a second end of the diode channel that is opposing the first end that is in contact with the first diode source/drain region.
4. The method of claim 1 , wherein the electrical device is a current mirror.
5. The method of claim 1 , wherein the electrical device is a comparator.
6. The method of claim 1 , wherein the electrical device is a sense amplifier.
7. The method of claim 1 , further comprising forming a first terminal to the electrically conductive region that simultaneously provides the first transistor source/drain region and the first diode source/drain region, and forming a second terminal in direct electrical contact to a second diode source/drain region.
8. The method of claim 1 , wherein the transistor gate structure is formed in a process that includes forming the dielectric spacer on the electrically conductive region, forming a transistor gate dielectric on the transistor channel region, and forming a gate conductor on the gate dielectric.
9. The method of claim 8 , wherein the transistor gate structure further comprises a work function adjusting metal layer.
10. The method of claim 8 , wherein the diode gate structure is formed by a sequence that includes forming a diode gate dielectric on the diode channel region and on a portion of the dielectric spacer that is present on the electrically conductive region in which the diode connected transistor device is formed, removing a portion of the dielectric spacer to expose the electrically conductive region including an overlying portion of the diode gate dielectric and forming a gate electrode.
11. The method of claim 10 , wherein the diode gate structure further comprises a work function adjusting metal layer.
12. A method of forming an electrical device comprising:
forming a transistor device in a first region of a substrate comprising a transistor channel, a first transistor source/drain region that is provided by an electrically conductive region at a first end of the transistor channel region, and a transistor gate structure that is separated from the first transistor source/drain region of the transistor by a dielectric spacer, wherein the transistor gate structure is formed in a process that includes forming the dielectric spacer on the electrically conductive surface, forming a transistor gate dielectric on the vertically orientated channel region, and forming a gate conductor on the gate dielectric; and
forming a diode connected transistor device in a second region of the substrate comprising a diode channel, a first diode source/drain region provided by the electrically conductive surface at a first end of the diode channel, and a diode gate structure in electrical contact with the first diode source/drain region, wherein the diode gate structure is formed by a sequence that includes forming a diode gate dielectric on the diode channel region and on a portion of the dielectric spacer that is present on the electrically conductive surface region in which the vertically orientated diode is formed.
13. The method of claim 12 , wherein the electrical device is a current mirror.
14. The method of claim 12 , wherein the electrical device is a comparator.
15. The method of claim 12 , wherein the electrical device is a sense amplifier.
16. The method of claim 12 , wherein the transistor gate structure further comprises a work function adjusting metal layer.
17. The method of claim 12 , wherein the diode gate structure further comprises a work function adjusting metal layer.
18. The method of claim 12 further comprising removing a portion of the dielectric spacer to expose the electrically conductive region including an overlying portion of the diode gate dielectric and forming a gate electrode.
19. The method of claim 12 , wherein the diode connected transistor device and the transistor device have substantially a same height.
20. The method of claim 19 , wherein the substrate is a semiconductor on insulator substrate, wherein the electrically conductive region is provided by an upper semiconductor layer of the semiconductor on insulator substrate.