IP Library › Granted Patent US 10,770,378

Granted Patent B1

US 10,770,378 · App. 16/401,828 · Granted Sep 8, 2020

Isolated component design

Inventor: Enis Tuncer (Dallas, TX)

Assignee: TEXAS INSTRUMENTS INCORPORATED

H01L23/49558 H01L23/49562

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Quick Facts

Patent No.: US 10,770,378
App. No.: 16/401,828
Granted: Sep 8, 2020
Kind: B1

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A microelectronic device includes a first conductor and a second conductor, separated by a lateral spacing. The first conductor has a low field contour facing the second conductor. The low field contour has offsets from a tangent line to the first conductor on the low field contour. Each of the offsets increases a separation of the high voltage conductor from the low voltage conductor. A first offset, located from an end of the high voltage conductor, at a first lateral distance of 25 percent of the minimum separation, is 19 percent to 28 percent of the minimum separation. A second offset, located at a second lateral distance of 50 percent of the minimum separation, is 9 percent to 14 percent of the minimum separation. A third offset, located at a third lateral distance of 75 percent of the minimum separation, is 4 percent to 6 percent of the minimum separation.

Claims (63)

1. A microelectronic device, comprising:

a first conductor;

a second conductor separated from the first conductor by a first lateral separation, the first lateral separation extending from a first straight tangent line that is tangent to the first conductor, to a second straight tangent line that is tangent to the second conductor, wherein:

the first conductor has a first low field contour along a side facing the second conductor;

the first straight tangent line is tangent to the first conductor on the first low field contour;

the first low field contour has a first offset from the first straight tangent line, the first offset being located at a first lateral distance of 25 percent of the first lateral separation from a first end of the first conductor, the first offset being 19 percent to 28 percent of the first lateral separation;

the first low field contour has a second offset from the first straight tangent line, the second offset being located at a second lateral distance of 50 percent of the first lateral separation from the first end of the first conductor, the second offset being 9 percent to 14 percent of the first lateral separation; and

the first low field contour has a third offset from the first straight tangent line, the third offset being located at a third lateral distance of 75 percent of the first lateral separation from the first end of the first conductor, the third offset being 4 percent to 6 percent of the first lateral separation.

2. The microelectronic device of claim 1 , wherein:

the second conductor has a second low field contour along a side facing the first conductor;

the second straight tangent line is tangent to the second conductor on the second low field contour;

the second low field contour has a first offset from the second straight tangent line, the first offset being located at a first lateral distance of 25 percent of the first lateral separation from a first end of the second conductor, the first offset being 19 percent to 28 percent of the first lateral separation;

the second low field contour has a second offset from the second straight tangent line, the second offset being located at a second lateral distance of 50 percent of the first lateral separation from the first end of the second conductor, the second offset being 9 percent to 14 percent of the first lateral separation; and

the second low field contour has a third offset from the second straight tangent line, the third offset being located at a third lateral distance of 75 percent of the first lateral separation from the first end of the second conductor, the third offset being 4 percent to 6 percent of the first lateral separation.

3. The microelectronic device of claim 2 , wherein the first end of the first conductor is aligned with the first end of the second conductor.

4. The microelectronic device of claim 2 , wherein:

the first low field contour has a fourth offset from the first straight tangent line, the fourth offset being located at a fourth lateral distance of 25 percent of the first lateral separation from a second end of the first conductor, the fourth offset being 19 percent to 28 percent of the first lateral separation;

the first low field contour has a fifth offset from the first straight tangent line, the fifth offset being located at a fifth lateral distance of 50 percent of the first lateral separation from the second end of the first conductor, the fifth offset being 9 percent to 14 percent of the first lateral separation; and

the first low field contour has a sixth offset from the first straight tangent line, the sixth offset being located at a sixth lateral distance of 75 percent of the first lateral separation from the second end of the first conductor, the sixth offset being 4 percent to 6 percent of the first lateral separation;

the second low field contour has a fourth offset from the second straight tangent line, the fourth offset being located at a fourth lateral distance of 25 percent of the first lateral separation from a second end of the second conductor, the fourth offset being 19 percent to 28 percent of the first lateral separation;

the second low field contour has a fifth offset from the second straight tangent line, the fifth offset being located at a fifth lateral distance of 50 percent of the first lateral separation from the second end of the second conductor, the fifth offset being 9 percent to 14 percent of the first lateral separation; and

the second low field contour has a sixth offset from the second straight tangent line, the sixth offset being located at a sixth lateral distance of 75 percent of the first lateral separation from the second end of the second conductor, the sixth offset being 4 percent to 6 percent of the first lateral separation.

5. The microelectronic device of claim 4 , wherein the second end of the first conductor is aligned with the second end of the second conductor.

6. The microelectronic device of claim 1 , wherein:

the first conductor has a first surface; and

the second conductor has a second surface, the second surface being coplanar with the first surface.

7. The microelectronic device of claim 1 , further comprising dielectric material between the first conductor and the second conductor.

8. The microelectronic device of claim 1 , further comprising a third conductor separated from the first conductor by a second lateral separation, the second lateral separation extending from a third straight tangent line that is tangent to the first conductor, to a fourth straight tangent line that is tangent to the third conductor, wherein:

the first conductor has a third low field contour along a side facing the third conductor;

the third straight tangent line is tangent to the first conductor on the third low field contour;

the third low field contour has a first offset from the third straight tangent line, the first offset being located at a first lateral distance of 25 percent of the second lateral separation from a third end of the first conductor, the first offset being 19 percent to 28 percent of the second lateral separation;

the third low field contour has a second offset from the third straight tangent line, the second offset being located at a second lateral distance of 50 percent of the second lateral separation from the third end of the first conductor, the second offset being 9 percent to 14 percent of the second lateral separation; and

the third low field contour has a third offset from the third straight tangent line, the third offset being located at a third lateral distance of 75 percent of the second lateral separation from the third end of the first conductor, the third offset being 4 percent to 6 percent of the second lateral separation.

9. The microelectronic device of claim 8 , wherein:

the third conductor has a fourth low field contour along a side facing the first conductor;

the fourth straight tangent line is tangent to the third conductor on the fourth low field contour;

the fourth low field contour has a first offset from the fourth straight tangent line, the first offset being located at a first lateral distance of 25 percent of the second lateral separation from a first end of the third conductor, the first offset being 19 percent to 28 percent of the second lateral separation;

the fourth low field contour has a second offset from the fourth straight tangent line, the second offset being located at a second lateral distance of 50 percent of the second lateral separation from the first end of the third conductor, the second offset being 9 percent to 14 percent of the second lateral separation; and

the fourth low field contour has a third offset from the fourth straight tangent line, the third offset being located at a third lateral distance of 75 percent of the second lateral separation from the first end of the third conductor, the third offset being 4 percent to 6 percent of the second lateral separation.

10. The microelectronic device of claim 8 , further comprising a fourth conductor separated from the second conductor by a third lateral separation, wherein:

the third lateral separation extends from a fifth straight tangent line that is tangent to the second conductor to a sixth straight tangent line that is tangent to the fourth conductor;

the second conductor has a fifth low field contour along a side facing the fourth conductor;

the fifth straight tangent line is tangent to the second conductor on the fifth low field contour;

the fifth low field contour has a first offset from the fifth straight tangent line, the first offset being located at a first lateral distance of 25 percent of the third lateral separation from a third end of the second conductor, the first offset being 19 percent to 28 percent of the third lateral separation;

the third low field contour has a second offset from the fifth straight tangent line, the second offset being located at a second lateral distance of 50 percent of the third lateral separation from the third end of the second conductor, the second offset being 9 percent to 14 percent of the third lateral separation; and

the third low field contour has a third offset from the fifth straight tangent line, the third offset being located at a third lateral distance of 75 percent of the third lateral separation from the third end of the second conductor, the third offset being 4 percent to 6 percent of the third lateral separation.

11. The microelectronic device of claim 10 , wherein:

the fourth conductor has a sixth low field contour along a side facing the second conductor;

the sixth straight tangent line is tangent to the fourth conductor on the sixth low field contour;

the sixth low field contour has a first offset from the sixth straight tangent line, the first offset being located at a first lateral distance of 25 percent of the third lateral separation from a first end of the fourth conductor, the first offset being 19 percent to 28 percent of the third lateral separation;

the sixth low field contour has a second offset from the sixth straight tangent line, the second offset being located at a second lateral distance of 50 percent of the third lateral separation from the first end of the fourth conductor, the second offset being 9 percent to 14 percent of the third lateral separation; and

the sixth low field contour has a third offset from the sixth straight tangent line, the third offset being located at a third lateral distance of 75 percent of the third lateral separation from the first end of the fourth conductor, the third offset being 4 percent to 6 percent of the third lateral separation.

12. The microelectronic device of claim 10 , wherein:

the first conductor has a first surface; and

the fourth conductor has a fourth surface, the fourth surface being coplanar with the first surface.

13. The microelectronic device of claim 1 , wherein the first conductor is part of a lead frame of the microelectronic device.

14. The microelectronic device of claim 13 , further comprising a first die attached to the first conductor.

15. The microelectronic device of claim 13 , wherein the first conductor includes a tie bar.

16. The microelectronic device of claim 13 , wherein the second conductor is part of the lead frame.

17. The microelectronic device of claim 16 , further comprising a second die attached to the second conductor.

18. The microelectronic device of claim 1 , wherein the first conductor and the second conductor are located in an interconnect region of the microelectronic device.

19. The microelectronic device of claim 18 , wherein the first conductor and the second conductor are plates of a capacitor of the microelectronic device.

20. The microelectronic device of claim 18 , wherein the first conductor and the second conductor are electrically coupled to active components of the microelectronic device.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2019

From: TUNCER, ENIS

To: TEXAS INSTRUMENTS INCORPORATED

Reel/Frame 049066/0093 →

Cited By (2)

US 12,191,252 US 12,660,671