Vertical modular stiffeners for stacked multi-device packages

1. A semiconductor device package, comprising:

a land-side semiconductor package substrate including a first surface and a second surface opposite the first surface;

a vertical-device stiffener on the land-side semiconductor package substrate, wherein the vertical-device stiffener includes a processor side and a radio-frequency side, wherein the vertical-device stiffener is on and orthogonal to the land-side semiconductor package substrate first surface, and wherein the vertical-device stiffener includes an insulated trace on the processor side;

a vertical semiconductive device on the vertical-device stiffener processor side, wherein the vertical semiconductive device is orthogonal to the land-side semiconductor package substrate first surface, and wherein the insulated trace is coupled to the vertical semiconductive device; and

a radio-frequency integrated circuit device on the vertical-device stiffener radio-frequency side.

2. The semiconductor device package of claim 1 , further including a stacked semiconductor-package substrate on the vertical-device stiffener, wherein the stacked semiconductor-package substrate includes a processor surface attached at the vertical-device stiffener; and

a semiconductive device on the stacked semiconductor-package substrate processor surface.

3. The semiconductor device package of claim 1 , wherein the vertical-device stiffener is a first vertical-device stiffener, further including:

a subsequent vertical-device stiffener on the land-side semiconductor package substrate first surface, wherein the subsequent vertical-device stiffer includes a processor side and a radio-frequency side, wherein the subsequent vertical-device stiffener is on and orthogonal to the land-side semiconductor package substrate first surface;

a subsequent vertical semiconductive device on the subsequent vertical-device stiffener processor side, wherein the subsequent vertical semiconductive device is orthogonal to the land-side semiconductor package substrate first surface; and

a subsequent radio-frequency integrated circuit device on the subsequent vertical-device stiffener radio-frequency side.

4. The semiconductor device package of claim 1 , wherein the vertical-device stiffener is a first vertical-device stiffener, further including:

a landed semiconductive device on the first surface;

a subsequent vertical-device stiffener on the land-side semiconductor package substrate first surface, wherein the subsequent vertical-device stiffer includes a processor side and a radio-frequency side, wherein the subsequent vertical-device stiffener is on and orthogonal to the land-side semiconductor package substrate first surface;

a subsequent vertical semiconductive device on the subsequent vertical-device stiffener processor side, wherein the subsequent vertical semiconductive device is orthogonal to the land-side semiconductor package substrate first surface;

a subsequent radio-frequency integrated circuit device on the subsequent vertical-device stiffener radio-frequency side;

a stacked semiconductor-package substrate on the first vertical-device stiffener and the subsequent vertical-device stiffener, wherein the stacked semiconductor-package substrate includes a processor surface attached at the first vertical-device stiffener and the subsequent vertical-device stiffener; and

a hanging semiconductive device on the stacked semiconductor-package substrate between the first vertical-device stiffener and the subsequent vertical-device stiffener.

5. The semiconductor device package of claim 1 , wherein the vertical-device stiffener includes a metallic core, further including a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the vertical semiconductive device, to the radio-frequency integrated circuit device.

6. The semiconductor device package of claim 1 , wherein the vertical-device stiffener includes a metallic core, further including:

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the vertical semiconductive device, to the radio-frequency integrated circuit device; and

a stacked semiconductive device on the vertical semiconductive device, wherein the vertical semiconductive device and the stacked semiconductive device are coupled by a through-silicon via interconnect in the vertical semiconductive device.

7. The semiconductor device package of claim 1 , wherein the vertical-device stiffener includes a metallic core, further including:

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the vertical semiconductive device, to the radio-frequency integrated circuit device;

a stacked semiconductive device on the vertical semiconductive device, wherein the vertical semiconductive device and the stacked semiconductive device are coupled by a through-silicon via interconnect in the vertical semiconductive device;

wherein the vertical semiconductive device is coupled on the processor side, between the land-side semiconductor package substrate and a stacked semiconductor-package substrate, with an insulated trace that couples to the land-side semiconductor package substrate, and an insulated trace that couples to the stacked semiconductor-package substrate.

8. The semiconductor device package of claim 7 , wherein the vertical-device stiffener includes a metallic core, further including:

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the vertical semiconductive device, to the radio-frequency integrated circuit device;

a stacked semiconductive device on the vertical semiconductive device, wherein the vertical semiconductive device and the stacked semiconductive device are coupled by a through-silicon via interconnect in the vertical semiconductive device;

wherein the radio-frequency integrated circuit device is coupled on the radio-frequency side, between the land-side semiconductor package substrate and the stacked semiconductor-package substrate, with an a first insulated trace of a first or subsequent vertical-device stiffener that couples to the land-side semiconductor package substrate, and an a second insulated trace of the first or subsequent vertical-device stiffener that couples to the stacked semiconductor-package substrate.

9. The semiconductor device package of claim 1 , wherein the vertical-device stiffener is a first vertical-device stiffener, further including:

a stacked semiconductor-package substrate on the first vertical-device stiffener, wherein the stacked semiconductor-package substrate includes a processor surface attached at the first vertical-device stiffener

a subsequent vertical-device stiffener on the land-side semiconductor package substrate first surface, wherein the subsequent vertical-device stiffer includes a processor side and a radio-frequency side, wherein the subsequent vertical-device stiffener is on and orthogonal to the land-side semiconductor package substrate first surface;

a subsequent vertical semiconductive device on the subsequent vertical-device stiffener processor side, wherein the subsequent vertical semiconductive device is orthogonal to the land-side semiconductor package substrate first surface;

a subsequent radio-frequency integrated circuit device on the subsequent vertical-device stiffener radio-frequency side; and

a radio-frequency integrated circuit device on the stacked semiconductor package substrate on a surface opposite the processor surface.

10. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core, further including a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to the subsequent radio-frequency integrated circuit device.

11. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core coupled to a reference voltage within the land-side semiconductor package substrate, further including a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to the subsequent radio-frequency integrated circuit device.

12. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core, further including:

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to the subsequent radio-frequency integrated circuit device;

wherein the subsequent vertical semiconductive device is coupled on the processor side, between the land-side semiconductor package substrate and the stacked semiconductor-package substrate, with a first, trace of the first or subsequent vertical-device stiffener that couples to the land-side semiconductor package substrate, and a second trace of the first or subsequent vertical-device stiffener that couples to the stacked semiconductor-package substrate.

13. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core, further including:

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to subsequent the radio-frequency integrated circuit device;

wherein the subsequent, radio-frequency integrated circuit device is coupled on the radio-frequency side, between the land-side semiconductor package substrate and the stacked semiconductor-package substrate, with a trace that couples to the land-side semiconductor package substrate, and a trace that couples to the stacked semiconductor-package substrate.

14. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core, further including:

a first semiconductive device on the first surface;

a subsequent bottom semiconductive device on the first surface and adjacent the first semiconductive device;

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to the subsequent radio-frequency integrated circuit device;

wherein the subsequent radio-frequency integrated circuit device is coupled on the radio-frequency side, between the land-side semiconductor package substrate and the stacked semiconductor-package substrate, with a first insulated trace of the first or subsequent vertical-device stiffener that couples to the land-side semiconductor package substrate, and an a second insulated trace of the first or subsequent vertical-device stiffener that couples to the stacked semiconductor-package substrate.

15. The semiconductor device package of claim 9 , wherein the subsequent vertical-device stiffener includes a metallic core, further including:

a first semiconductive device on the first surface;

a subsequent bottom semiconductive device on the first surface and adjacent the first semiconductive device;

a through-stiffener via that passes through the metallic core, wherein the through-stiffener via couples the subsequent vertical semiconductive device, to the subsequent radio-frequency integrated circuit device;

wherein the subsequent radio-frequency integrated circuit device is coupled on the radio-frequency side, between the land-side semiconductor package substrate and the stacked semiconductor-package substrate, with a trace that couples to the land-side semiconductor package substrate, and a trace that couples to the stacked semiconductor-package substrate; and

a hanging semiconductor device on the stacked semiconductor package substrate at the processor side.

16. The semiconductor device package of claim 1 , further including:

a board contacting the land-side semiconductor package substrate at the second surface;

a bottom semiconductive device on the land-side semiconductor package substrate at the first surface; and

wherein the bottom semiconductive device is part of a chipset in a computing system.

17. A stacked multi-chip package, comprising:

a land-side semiconductor package substrate including a first surface and a second surface opposite the first surface;

a landed semiconductive device on the first surface;

a first vertical-device stiffener including a first side and a second side, and wherein the first vertical-device stiffener includes an insulated trace on the first side;

a first semiconductive device on the first vertical-device stiffener first side;

a subsequent vertical-device stiffener, wherein the first and subsequent vertical-device stiffeners are spaced apart by the landed semiconductive device;

a stacked semiconductor package substrate including a semiconductive device side and a radio side, wherein the stacked semiconductor package substrate contacts each of the first vertical-device stiffener, and the subsequent vertical-device stiffener on the semiconductive device side; and

a semiconductive device on the stacked semiconductor package substrate semiconductive device side.

18. The stacked multi-chip package of claim 17 , further including:

a third vertical-device stiffener on the first surface, wherein the third vertical-device stiffener includes a first side and a second side, and wherein the third vertical-device stiffener includes an insulated trace on the first side;

a fourth vertical-device stiffener on the first surface, wherein the third and fourth vertical-device stiffeners are arrayed on the first surface and are spaced apart by the landed semiconductive device.

19. The stacked multi-chip package of claim 17 , further including:

a first radio-frequency device on the first vertical-device stiffener second side, wherein a through-stiffener via passes through the first vertical-device stiffener and couples the first semiconductive device and the first radio-frequency device;

a third vertical-device stiffener on the first surface, wherein the third vertical-device stiffener includes a first side and a second side, and wherein the third vertical-device stiffener includes an insulated trace on the first side;

a fourth vertical-device stiffener on the first surface, wherein the third and fourth vertical-device stiffeners are arrayed on the first surface across from a bottom semiconductive device.

20. The stacked multi-chip package of claim 17 , further including a radio-frequency, device on the stacked semiconductor package substrate on the radio side.

21. A process of assembling a stacked multiple-chip package, comprising:

assembling a semiconductive device to a vertical-device stiffener on a first side of the vertical device stiffener, to couple the semiconductive device to an insulated trace on the first side of the vertical device stiffener,

assembling the vertical-device stiffener orthogonally to a first surface of a land-side semiconductor package substrate, wherein the first surface carries a bottom semiconductive device; and

assembling a stacked semiconductor package substrate orthogonally at a semiconductor device side to the vertical-device stiffener, wherein the semiconductor device side carries a hanging semiconductive device.

22. The process of claim 21 , wherein the vertical-device stiffener includes a second side, further including assembling a radio-frequency device to the vertical-device stiffener on the second side, to couple to an embedded trace on the second side.

23. The process of claim 21 , wherein the vertical-device stiffener is a first vertical-device stiffener, further including:

assembling a subsequent semiconductive device to a subsequent vertical-device stiffener on a first side of the subsequent vertical device stiffener, to couple the subsequent semiconductive device to an insulated trace on the first side of the subsequent vertical device stiffener; and

assembling the subsequent vertical-device stiffener orthogonally to the first surface of the land-side semiconductor package substrate, wherein the first and subsequent vertical-device stiffeners are spaced apart by the bottom semiconductive device.

24. The process of claim 23 , wherein the subsequent vertical-device stiffener includes a second side, further including assembling a subsequent radio-frequency device to the subsequent vertical-device stiffener on the second side, to couple to an embedded trace on the second side.