Push-pull dynamic amplifier circuits
A push-pull dynamic amplifier is operable in reset and amplification phases. The amplifier includes first NMOS and PMOS input transistors that are electrically coupled to a first input terminal and a first output terminal. Second NMOS and PMOS input transistors are electrically coupled to a second input terminal and a second output terminal. First and second reset switches are electrically coupled to the first and second output terminals, respectively. A power supply switch is electrically coupled to the first and the second PMOS transistors, and a ground switch is electrically coupled to the first and the second NMOS transistors. During the reset phase, the reset switches are closed and the power supply switch and the ground switch are opened. During the amplification phase, the reset switches are opened and the power supply switch and the ground switch are closed.
1. A dynamic amplifier operable in a reset phase and an amplification phase, comprising:
a power supply having a first voltage level;
a reset voltage source having a second voltage level between a ground level and the first voltage level;
a first and a second input terminal;
a first and a second output terminal;
a first NMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second NMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first PMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second PMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the reset voltage source;
a second reset switch electrically coupled to the second output terminal and the reset voltage source;
a power supply switch electrically coupled to the first and the second PMOS input transistors and to the power supply; and
a ground switch electrically coupled to the first and the second NMOS input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.
2. The amplifier of claim 1 , wherein:
a first input voltage is electrically coupled to the first input terminal, and
a second input voltage is electrically coupled to the second input terminal.
3. The amplifier of claim 2 , wherein:
the power supply switch comprises a PMOS transistor, and
the ground switch comprises an NMOS transistor.
4. The amplifier of claim 3 , wherein an average current of the first and the second PMOS transistors is substantially equal to an average current of the first and the second NMOS transistors.
5. The amplifier of claim 3 , wherein sizes of the first and the second PMOS input transistors are configured such that an average current of the first and the second PMOS transistors is substantially equal to an average current of the first and the second NMOS transistors.
6. The amplifier of claim 1 , wherein the power supply switch and the ground switch are turned off at the end of the amplification phase.
7. The amplifier of claim 1 , further comprising:
a first sampling capacitor; and
a first input switch electrically coupled to the first sampling capacitor and a first input voltage.
8. The amplifier of claim 7 , further comprising a first sampling switch electrically coupled to the first input terminal.
9. The amplifier of claim 8 , further comprising a first reference switch electrically coupled to the first sampling capacitor.
10. The amplifier of claim 9 , wherein the first input switch is closed during the reset phase and opened during the amplification phase.
11. The amplifier of claim 10 , wherein the first reference switch is opened during the reset phase and closed during the amplification phase.
12. The amplifier of claim 9 , wherein the first reference switch is electrically coupled to a first reference voltage.
13. The amplifier of claim 7 , further comprising:
a second sampling capacitor; and
a second input switch electrically coupled to the second sampling capacitor and a second input voltage.
14. The amplifier of claim 13 , further comprising:
a first sampling switch electrically coupled to the first input terminal; and
a second sampling switch electrically coupled to the second input terminal.
15. The amplifier of claim 14 , further comprising:
a first reference switch electrically coupled to the first sampling capacitor; and
a second reference switch electrically coupled to the second sampling capacitor.
16. The amplifier of claim 15 , wherein the first and the second input switches are closed during the reset phase and opened during the amplification phase.
17. The amplifier of claim 16 , wherein the first and the second reference switches are opened during the reset phase and closed during the amplification phase.
18. The amplifier of claim 15 , wherein:
the first reference switch is electrically coupled to a first reference voltage, and
the second reference switch is electrically coupled to a second reference voltage.
19. The amplifier of claim 7 , wherein:
the first reset switch is electrically coupled to the first input terminal, and
the second reset switch is electrically coupled to the second input terminal.
20. A dynamic amplifier operable in a reset phase and an amplification phase, comprising:
a power supply having a first voltage level;
a reset voltage source having a second voltage level between a ground level and the first voltage level;
a first, a second, a third, and a fourth input terminal;
a first and a second output terminal;
a first input transistor electrically coupled to the first input terminal and the first output terminal;
a second input transistor electrically coupled to the second input terminal and the second output terminal;
a third input transistor electrically coupled to the third input terminal and the first output terminal;
a fourth input transistor electrically coupled to the fourth input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the reset voltage source;
a second reset switch electrically coupled to the second output terminal and the reset voltage source;
a power supply switch electrically coupled to the third and fourth input transistors and to the power supply; and
a ground switch electrically coupled to the first and the second input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.
21. The amplifier of claim 20 , further comprising:
a first sampling capacitor electrically coupled to the first input terminal;
a second sampling capacitor electrically coupled to the second input terminal;
a first input switch electrically coupled to the first sampling capacitor and a first input voltage; and
a second input switch electrically coupled to the second sampling capacitor and a second input voltage.
22. The amplifier of claim 21 , further comprising:
a third sampling capacitor electrically coupled to the third input terminal;
a fourth sampling capacitor electrically coupled to the fourth input terminal;
a third input switch electrically coupled to the third sampling capacitor and the first input voltage; and
a fourth input switch electrically coupled to the fourth sampling capacitor and the second input voltage.
23. The amplifier of claim 22 wherein:
the first reset switch is electrically coupled to the third input terminal, and
the second reset switch is electrically coupled to the fourth input terminal.
24. The amplifier of claim 22 , wherein:
the first reset switch is electrically coupled to the first input terminal, and
the second reset switch is electrically coupled to the second input terminal.
25. A dynamic amplifier operable in a reset phase and an amplification phase, comprising:
a first and a second input terminal;
a first and a second output terminal;
a first NMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second NMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first PMOS input transistor electrically coupled to the first input terminal and the first output terminal;
a second PMOS input transistor electrically coupled to the second input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the first input terminal;
a second reset switch electrically coupled to the second output terminal and the second input terminal;
a power supply switch electrically coupled to the first and the second PMOS input transistors; and
a ground switch electrically coupled to the first and the second NMOS input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.
26. The amplifier of claim 25 , wherein:
a first input voltage is electrically coupled to the first input terminal, and
a second input voltage is electrically coupled to the second input terminal.
27. The amplifier of claim 26 , wherein:
the power supply switch comprises a PMOS transistor, and the ground switch comprises an NMOS transistor.
28. The amplifier of claim 27 , wherein an average current of the first and the second PMOS transistors is substantially equal to an average current of the first and the second NMOS transistors.
29. The amplifier of claim 27 , wherein sizes of the first and the second PMOS input transistors are configured such that an average current of the first and the second PMOS transistors is substantially equal to an average current of the first and the second NMOS transistors.
30. The amplifier of claim 28 , wherein the first and the second reset switches are electrically coupled to a reset voltage.
31. The amplifier of claim 25 , wherein the power supply switch and the ground switch are turned off at the end of the amplification phase.
32. The amplifier of claim 25 , further comprising:
a first sampling capacitor; and
a first input switch electrically coupled to the first sampling capacitor and a first input voltage.
33. The amplifier of claim 32 , further comprising a first sampling switch electrically coupled to the first input terminal.
34. The amplifier of claim 33 , further comprising a first reference switch electrically coupled to the first sampling capacitor.
35. The amplifier of claim 34 , wherein the first input switch is closed during the reset phase and opened during the amplification phase.
36. The amplifier of claim 35 , wherein the first reference switch is opened during the reset phase and closed during the amplification phase.
37. The amplifier of claim 34 , wherein the first reference switch is electrically coupled to a first reference voltage.
38. The amplifier of claim 32 , further comprising:
a second sampling capacitor; and
a second input switch electrically coupled to the second sampling capacitor and a second input voltage.
39. The amplifier of claim 38 , further comprising:
a first sampling switch electrically coupled to the first input terminal; and
a second sampling switch electrically coupled to the second input terminal.
40. The amplifier of claim 39 , further comprising:
a first reference switch electrically coupled to the first sampling capacitor; and
a second reference switch electrically coupled to the second sampling capacitor.
41. The amplifier of claim 40 , wherein the first and the second input switches are closed during the reset phase and opened during the amplification phase.
42. The amplifier of claim 41 , wherein the first and the second reference switches are opened during the reset phase and closed during the amplification phase.
43. The amplifier of claim 40 , wherein:
the first reference switch is electrically coupled to a first reference voltage, and
the second reference switch is electrically coupled to a second reference voltage.
44. The amplifier of claim 42 , wherein:
the first reset switch is electrically coupled to the first input terminal, and
the second reset switch is electrically coupled to the second input terminal.
45. A dynamic amplifier operable in a reset phase and an amplification phase, comprising:
a first, a second, a third, and a fourth input terminal;
a first and a second output terminal;
a first input transistor electrically coupled to the first input terminal and the first output terminal;
a second input transistor electrically coupled to the second input terminal and the second output terminal;
a third input transistor electrically coupled to the third input terminal and the first output terminal;
a fourth input transistor electrically coupled to the fourth input terminal and the second output terminal;
a first reset switch electrically coupled to the first output terminal and the first input terminal;
a second reset switch electrically coupled to the second output terminal and the second input terminal;
a power supply switch electrically coupled to the third and fourth input transistors; and
a ground switch electrically coupled to the first and the second input transistors;
wherein:
during the reset phase:
the first and the second reset switches are closed, and
the power supply switch and the ground switch are opened, and
during the amplification phase:
the first and the second reset switches are opened, and
the power supply switch and the ground switch are closed.
46. The amplifier of claim 45 , further comprising:
a first sampling capacitor electrically coupled to the first input terminal;
a second sampling capacitor electrically coupled to the second input terminal;
a first input switch electrically coupled to the first sampling capacitor and a first input voltage; and
a second input switch electrically coupled to the second sampling capacitor and a second input voltage.
47. The amplifier of claim 46 , further comprising:
a third sampling capacitor electrically coupled to the third input terminal;
a fourth sampling capacitor electrically coupled to the fourth input terminal;
a third input switch electrically coupled to the third sampling capacitor and the first input voltage; and
a fourth input switch electrically coupled to the fourth sampling capacitor and the second input voltage.