Amplifier and electronic system including the same
An amplifier and an electronic system including the same are provided. An amplifier includes a first NMOS transistor configured to receive a first input, a second NMOS transistor configured to receive a second input, the second NMOS transistor including a source connected to a source of the first NMOS transistor, a first resistor including a first end connected to a drain of the first NMOS transistor and a second end connected to a first output, a second resistor including a first end connected to a drain of the second NMOS transistor, and a second end connected to a second output, and the amplifier is configured to generate the first output and the second output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.
1 . An amplifier comprising:
a first sub-dynamic amplifier; and
a second sub-dynamic amplifier;
the first sub-dynamic amplifier including:
a first-a NMOS transistor configured to receive a first input;
a second-a NMOS Transistor configured to receive a second input, the second-a NMOS transistor including a source connected to a source of the first-a NMOS transistor;
a first resistor including a first end connected to a drain of the first-a NMOS transistor and a second end connected to a first-a output;
a second resistor including a first end connected to a drain of the second-a NMOS Transistor, and a second end connected to a second-a output, and
the second sub-dynamic amplifier including:
a first-b NMOS transistor configured to receive an output of a drain of the first-a NMOS transistor, the first-b NMOS transistor including a drain connected to a first-b output;
a second-b NMOS transistor configured to receive an output of a drain of the second-a NMOS transistor, the second-b NMOS transistor including a source connected to a source of the first-b NMOS transistor, and the drain of the second-b NMOS transistor is connected to a second-b output, and
wherein the amplifier is configured to generate the first-b output and the second-b output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor,
wherein the first-a output and the second-a output are connected to a first reset switch block, and the first reset switch block is configured to reset the first-a output and the second-a output to a common voltage,
wherein the first-b output and the second-b output are connected to a second reset switch block, and the second reset switch block is configured to reset the first-b output and the second-b output to the common voltage.
2 . The amplifier of claim 1 , wherein the resistance values of the first resistor and the second resistor are equal to each other.
3 . The amplifier of claim 1 , wherein the resistance values of the first resistor and the second resistor are different from each other.
4 . The amplifier of claim 1 , wherein the amplifier further comprises: a third resistor connected to the first-a output;
a fourth resistor connected to the second-a output;
a first-a PMOS transistor connected in series with the third resistor, the first-a PMOS transistor configured to receive the first input; and
a second-a PMOS transistor connected in series with the fourth resistor, the second-a PMOS transistor including a source connected to a source of the first-a PMOS transistor, and the second-a PMOS transistor is configured to receive the second input.
5 . The amplifier of claim 4 , wherein the resistance values of the first resistor and the second resistor and resistance values of the third resistor and the fourth resistor are equal to each other.
6 . The amplifier of claim 4 , wherein the resistance values of the first resistor and the second resistor and resistance values of the third resistor and the fourth resistor are different from each other.
7 . The amplifier of claim 4 , wherein
the resistance values of each of the first resistor and the second resistor is equal to a first resistance value; and
resistance values of each of the third resistor and the fourth resistor is equal to a second resistance value different from the first resistance value.
8 . The amplifier of claim 1 , wherein the first sub-dynamic amplifier further includes:
a first-a PMOS transistor including a source configured to receive a power voltage,
a second-a PMOS transistor including a source configured to receive the power voltage, and
wherein the sources of the first-a PMOS transistor and the second-a PMOS transistor are connected to each other, and
wherein the second sub-dynamic amplifier further includes:
a first-b PMOS transistor including a drain and a source, the drain connected to the first-b output, and the source configured to receive the power voltage, and
a second-b PMOS transistor including a drain and a source, the drain connected to the second-b output, and the source configured to receive the power voltage, and
wherein the sources of the first-b PMOS transistor and the second-b PMOS transistor are connected to each other.
9 . An amplifier comprising:
a first sub-dynamic amplifier; and
a second sub-dynamic amplifier;
the first sub-dynamic amplifier including:
a first-a NMOS transistor configured to receive a first input,
a second-a NMOS transistor configured to receive a second input, the second-a NMOS transistor including a source connected to a source of the first-a NMOS transistor,
a first resistor including a first end connected to a drain of the first-a NMOS transistor and a second end connected to a first-a output, and
a second resistor including a first end connected to a drain of the second-a NMOS transistor and a second end connected to a second-a output;
the second sub-dynamic amplifier including:
a first-b NMOS transistor configured to receive an output of a drain of the first-a NMOS transistor, the first-b NMOS transistor including a drain connected to a first-b output;
a second-b NMOS transistor configured to receive an output of a drain of the second-a NMOS transistor, the second-b NMOS transistor including a source connected to a source of the first-b NMOS transistor, and the drain of the second-b NMOS transistor is connected to a second-b output; and
wherein the first sub-dynamic amplifier further includes:
a first-a PMOS transistor including a source configured to receive a power voltage, and
a second-a PMOS transistor including a source configured to receive the power voltage,
wherein the sources of the first-a PMOS transistor and the second-a PMOS transistor are connected to each other, and
wherein the amplifier is configured to generate the first-b output and the second-b output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.
10 . The amplifier of claim 9 , wherein the resistance values of the first resistor and the second resistor are equal to each other.
11 . The amplifier of claim 9 , wherein the resistance values of the first resistor and the second resistor are different from each other.
12 . The amplifier of claim 9 , wherein
the second sub-dynamic amplifier further includes:
a first-b PMOS transistor including a drain and a source, the drain connected to the first-b output, and the source configured to receive the power voltage, and
a second-b PMOS transistor including a drain and a source, the drain connected to the second-b output, and the source configured to receive the power voltage,
wherein the sources of the first-b PMOS transistor and the second-b PMOS transistor are connected to each other.
13 . The amplifier of claim 9 , wherein the first sub-dynamic amplifier further includes:
a third resistor connected to the first-a output; and
a fourth resistor connected to the second-a output.
14 . The amplifier of claim 13 , wherein the resistance values of the first resistor and the second resistor, and resistance values of the third resistor and the fourth resistor are equal to each other.
15 . The amplifier of claim 13 , wherein the resistance values of the first resistor and the second resistor, and resistance values of the third resistor and the fourth resistor are different from each other.
16 . The amplifier of claim 13 , wherein
the resistance values of each of the first resistor and the second resistor are equal to a first resistance value; and
resistance values of each of the third resistor and the fourth resistor are equal to a second resistance value different from the first resistance value.
17 . The amplifier of claim 13 , wherein
the first-a output and the second-a output are connected to a first reset switch block; the first reset switch block is configured to reset the first-a output and the second-a output to a common voltage;
the first-b output and the second-b output are connected to a second reset switch block; and
the second reset switch block is configured to reset the first-b output and the second-b output to the common voltage.
18 . An electronic system comprising:
at least one processor;
a communication interface configured to communicate with the at least one processor, the communication interface including the amplifier according to claim 9 .
19 . The electronic system of claim 18 , wherein the first sub-dynamic amplifier further includes:
a third resistor connected to the first-a output; and
a fourth resistor connected to the second-a output;
wherein the first-a PMOS transistor is connected in series with the third resistor; and
wherein the second-a PMOS transistor is connected in series with the fourth resistor.
20 . The electronic system of claim 18 , wherein the second sub-dynamic amplifier further includes:
a first-b PMOS transistor including a drain and a source, the drain connected to the first-b output, and the source configured to receive the power voltage, and
a second-b PMOS transistor including a drain and a source, the drain connected to the second-b output, and the source configured to receive the power voltage, and wherein the sources of the first-b PMOS transistor and the second-b PMOS transistor are connected to each other.