Apparatuses including test segment circuits having latch circuits for testing a semiconductor die
Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.
1. An apparatus, comprising:
a plurality of segment lines configured to form a ring around a die, each segment line comprising:
a portion of a first signal line;
a portion of a second signal line; and
a portion of a third signal line; and
a plurality of test segment circuits, each test segment circuit coupled to at leastwo segment lines of the plurality of segment lines,
each test segment circuit coupled to the portion of the first signal line, the portion of the second signal line, and the portion of the third signal line, and
each test segment circuit configured to control an operation performed on at least one segment line of the plurality of segment lines, wherein each test segment circuit further comprises:
a respective first latch circuit configured to activate a respective test segment circuit based on a first signal; and
a respective second latch circuit configured to activate an adjacent test segment circuit to the respective test segment circuit.
2. The apparatus of claim 1 , wherein the respective first latch circuit is further configured to receive a second signal that clocks the respective test segment circuit.
3. The apparatus of claim 2 , wherein the respective second latch circuit is further configured to transmit a third signal that activates the adjacent test segment circuit to the respective test segment circuit.
4. The apparatus of claim 3 , wherein the respective first latch circuit further configured to receive a fourth signal that enables testing of each segment line of the plurality of segment lines, and wherein the respective second latch circuit further configured to receive an inverted version of the fourth signal.
5. The apparatus of claim 4 , wherein each test segment circuit further comprises:
a transistor configured to receive, at a gate of the transistor, a fifth signal from the respective first latch circuit.
6. The apparatus of claim 5 , wherein each test segment circuit further comprises
a switch, coupled to the transistor, configured to receive a sixth signal from the respective first latch circuit, the sixth signal configured to activate the switch.
7. The apparatus of claim 6 , wherein each test segment circuit coupled to a respective portion of the second signal line via a coupling to the switch.
8. The apparatus of claim 5 , wherein each test segment circuit coupled to the respective portion of the second signal line via a coupling to the transistor.
9. The apparatus of claim 5 , wherein the respective portion of the second signal line is configured to supply the transistor when the fifth signal activates a pull-down mode of the transistor.
10. The apparatus of claim 9 , wherein, when the fifth signal activates the pull-down mode of the transistor, a die crack detection circuit is configured to test a head portion or a tail portion of the second signal line for a die crack in the die.
11. The apparatus of claim 1 , wherein each test segment circuit coupled to a respective portion of the third signal line via a coupling to the respective first latch circuit.
12. An apparatus, comprising:
a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of a plurality of segment lines, a first signal line, a second signal line, and a third signal line, each test segment circuit comprising:
a first latch circuit configured to activate a respective test segment circuit based on a first signal; and
a second latch circuit configured to activate an adjacent test segment circuit to the respective test segment circuit;
a switch configured to receive a second signal from the first latch circuit, the second signal configured to activate the switch; and
a transistor coupled to the switch, the transistor configured to receive a third signal that activates a pull-down mode of the transistor,
wherein each test segment circuit configured to control an operation performed on at least one segment line of the plurality of segment lines.
13. The apparatus of claim 12 , wherein the third signal line is configured to drive an enable signal to the first latch circuit of each test segment circuit.
14. The apparatus of claim 13 , wherein each test segment circuit further comprising:
an inverter configured to receive an inverted enable signal that activates the second latch circuit.
15. The apparatus of claim 12 , wherein each test segment circuit further comprising:
a NAND gate, and wherein the first signal line is configured to drive a clock signal to the NAND gate of each test segment circuit.
16. The apparatus of claim 12 , further comprising:
a die crack detection circuit configured to drive a voltage on the second signal line to test the die for a die crack, wherein the second signal line is configured to drive the voltage to the transistor or the switch of each test segment circuit.
17. The apparatusof claim 16 , the die crack detection circuit comprising:
a first switch coupled to a head segment line of the plurality of segment lines;
a second switch coupled to a tail segment line of the plurality of segment lines;
a third switch coupled to the first switch and coupled to the tail segment line; and
a fourth switch coupled to the second switch and coupled to the head segment line.
18. An apparatus, comprising:
a plurality of segment lines configured to form around a die, each segment line comprising portions of a plurality of signal lines;
a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines, wherein each test segment circuit configured to control an operation performed on at least one segment line of the plurality of segment lines, wherein each test segment circuit comprises:
a respective first latch circuit configured to activate a respective test segment circuit based on a first signal; and
a respective second latch circuit configured to activate an adjacent test segment circuit to the respective test segment circuit.
19. The apparatus of claim 18 , wherein the respective first latch circuit is further configured to receive a second signal that clocks the respective test segment circuit, and wherein the respective second latch circuit is further configured to transmit a third signal that activates the adjacent test segment circuit to the respective test segment circuit.
20. The apparatus of claim 18 , wherein each test segment circuit is coupled to a respective portion of a first signal line of the plurality of signal lines, a respective portion of a second signal line of the plurality of signal lines, and a respective portion of a third signal line of the plurality of signal lines.