Memory component that enables calibrated command- and data-timing signal arrival
A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.
1. A method of operation within an integrated circuit memory (“memory IC”), the method comprising:
receiving a first timing signal from a memory controller via a first timing signal line;
performing a timing calibration operation, including (i) receiving a sequence of differently delayed calibration timing signals from the memory controller via a second timing signal line, and (ii) outputting, to the memory controller, signals corresponding to the sequence of differently delayed calibration timing signals to enable the memory controller to determine a write timing delay; and
receiving signals from the memory controller for a write operation, including (i) sampling address/control signals at one or more times indicated by the first timing signal, (ii) receiving, via the second timing signal line, a write data timing signal delayed according to the write timing delay, and (iii) receiving write data signals at one or more times indicated by the write data timing signal.
2. The method of claim 1 further comprising storing, within a memory array of the memory IC at a location indicated by the address/control signals, write data conveyed in the write data signals.
3. The method of claim 1 wherein receiving the write data signals comprises receiving the write data signals via one or more data signal lines, and wherein receiving the write data timing signal comprises receiving a write data strobe signal.
4. The method of claim 3 wherein receiving the first timing signal from the memory controller comprises receiving a first clock signal.
5. The method of claim 3 wherein receiving the write data signals via one or more data signal lines comprises receiving a plurality of write data signals in parallel via a plurality of data signal lines.
6. The method of claim 1 wherein receiving the sequence of differently delayed calibration timing signals from the memory controller via a second timing signal line comprises receiving calibration timing signals having respective phases substantially evenly distributed within a predetermined time interval.
7. The method of claim 6 wherein receiving calibration timing signals having respective phases substantially evenly distributed within the predetermined time interval comprises receiving calibration timing signals having respective phases substantially evenly distributed within a time interval that commences at a first transition of the first timing signal and that concludes at a second transition of the first timing signal.
8. The method of claim 1 wherein performing the timing calibration operation further includes receiving respective dummy-write data signals corresponding to each of the differently delayed calibration timing signals.
9. The method of claim 8 wherein performing the timing calibration operation further includes (i) storing, within a memory array of the memory IC, dummy-write data corresponding respectively to the dummy-write data signals, and (ii) reading the dummy-write data out of the memory array to be output as the signals corresponding to the sequence of differently delayed calibration timing signals.
10. The method of claim 9 wherein performing the timing calibration operation further includes receiving a plurality of commands associated respectively with the differently delayed calibration timing signals and indicating that the dummy-write data is to be stored within the memory array and read out of the memory array.
11. An integrated circuit memory (“memory IC”) comprising:
a first timing signal interface to receive a first timing signal from a memory controller;
a second timing signal interface;
an address/control signal interface;
a data signal interface; and
control circuitry to:
receive, via the second timing signal interface during a timing calibration operation, a sequence of differently delayed calibration timing signals;
output, to the memory controller during the timing calibration operation, signals corresponding to the sequence of differently delayed calibration timing signals to enable the memory controller to determine a write timing delay;
receive, via the address/control signal interface during a memory write operation, address/control signals at one or more times indicated by the first timing signal;
receive, via the second timing signal interface during the memory write operation, a write data timing signal delayed according to the write timing delay, and
receive, via the data signal interface during the memory write operation, write data signals at one or more times indicated by the write data timing signal.
12. The memory IC of claim 11 further comprising a memory array, and wherein the control circuitry is further to store, within the memory array at a location indicated by the address/control signals, write data conveyed in the write data signals.
13. The memory IC of claim 1 wherein the control circuitry to receive the write data timing signal during the memory write operation comprises circuitry to receive a write data strobe signal.
14. The memory IC of claim 13 wherein the first timing signal interface to receive the first timing signal from the memory controller comprises an interface to receive a first clock signal from the memory controller.
15. The memory IC of claim 13 wherein the control circuitry to receive the write data signals via the data signal interface during the memory write operation comprises circuitry to sample a plurality of write data signals in parallel.
16. The memory IC of claim 11 wherein the control circuitry to receive the sequence of differently delayed calibration timing signals from the memory controller via a second timing signal interface during the timing calibration operation comprises circuitry to receive calibration timing signals having respective phases substantially evenly distributed within a predetermined time interval.
17. The memory IC of claim 16 wherein the circuitry to receive calibration timing signals having respective phases substantially evenly distributed within the predetermined time interval comprises circuitry to receive calibration timing signals having respective phases substantially evenly distributed within a time interval that commences at a first transition of the first timing signal and that concludes at a second transition of the first timing signal.
18. The memory IC of claim 11 wherein the control circuitry is further to receive, via the data signal interface during the timing calibration operation, respective dummy-write data signals corresponding to each of the differently delayed calibration timing signals.
19. The memory IC of claim 18 further comprising a memory array, and wherein, during the timing calibration operation, the control circuitry is further to (i) store, within the memory array, dummy-write data corresponding respectively to the dummy-write data signals, and (ii) read the dummy-write data out of the memory array to be output as the signals corresponding to the sequence of differently delayed calibration timing signals.
20. An integrated circuit memory comprising:
a first timing signal interface to receive a first timing signal from a memory controller;
an address control signal interface to receive address/control signals at one or more times indicated by the first timing signal;
a second timing signal interface to receive, during a timing calibration operation, a sequence of differently delayed calibration timing signals; and
a data signal interface to output, to the memory controller during the timing calibration operation, signals corresponding to the sequence of differently delayed calibration timing signals.