OPEN PAD STRUCTURE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

1 . An open pad structure, comprising:

an insulating layer;

a first pad disposed on the insulating layer;

a second pad disposed on the insulating layer and spaced apart from the first pad; and

a passivation layer disposed on the insulating layer, covering the first and second pads, and having an opening for opening at least a portion of each of the first and second pads, wherein the passivation layer covers the insulating layer between the first and second pads in the opening, and wherein t 1 and t 2 satisfy t 1 >t 2 , in which t 1 is a thickness of a region of the passivation layer other than the opening, and t 2 is a thickness of a region of the passivation layer between the first and second pads.

2 . The open pad structure of claim 1 , wherein t 2 , t 3 , and t 4 satisfy t 2 ≥t 3 and t 2 ≥t 4 , in which t 3 is a thickness of the first pad and t 4 is a thickness of the second pad.

3 . The open pad structure of claim 2 , wherein a, b, and c satisfy a≥c and b≥c, in which a is a depth of the opening to an exposed surface of the first pad, b is a depth of the opening to an exposed surface of the second pad, and c is a depth of the opening to an exposed surface of the passivation layer between the first and second pads.

4 . The open pad structure of claim 1 , wherein the passivation layer includes a thermosetting resin.

5 . The open pad structure of claim 1 , wherein the opening includes a first opening exposing at least a portion of a surface of the first pad, a second opening exposing at least a portion of a surface of the second pad, and a third opening penetrating a portion of the passivation layer between the first and second pads and exposing a surface of the passivation layer between the first and second pads.

6 . The open pad structure of claim 1 , further comprising:

an electronic component disposed on the passivation layer, and having first and second external electrodes connected to the first and second pads, respectively.

7 . The open pad structure of claim 6 , wherein the first and second pads and the first and second external electrodes are connected to each other by a solder.

8 . The open pad structure of claim 1 , wherein the passivation layer covers an edge of a surface of each of the first and second pads.

9 . The open pad structure of claim 8 , wherein regions of the passivation layer covering edges of surfaces of the first and second pads have a first region having a thickness substantially the same as a thickness of the region between the first and second pads, and a second region having a thickness greater than the thickness of the region between the first and second pads.

10 . The open pad structure of claim 8 , wherein regions of the passivation layer covering edges of surfaces of the first and second pads have thicknesses substantially the same as a thickness of the region between the first and second pads.

11 . The open pad structure of claim 10 , wherein the opening has a plurality of stepped portions disposed across exposed surfaces of the first and second pads, exposed surfaces of the passivation layer covering edges of surfaces of the first and second pads, and a surface of the passivation layer other than the opening.

12 . The open pad structure of claim 1 , wherein the region of the passivation layer having the thickness t 1 is disposed directly on the insulating layer.

13 . A semiconductor package, comprising:

a semiconductor chip having a connection pad;

an encapsulant covering at least a portion of the semiconductor chip;

an interconnect structure disposed on the semiconductor chip and the encapsulant and including a redistribution layer electrically connected to the connection pad; and

a passivation layer disposed on the interconnect structure and covering at least a portion of the redistribution layer,

wherein the redistribution layer includes first and second pads spaced apart from each other,

wherein the passivation layer has an opening exposing at least a portion of each of the first and second pads,

wherein the passivation layer covers the interconnect structure between the first and second pads in the opening, and

wherein t 1 and t 2 satisfy t 1 >t 2 , in which t 1 is a thickness of a region of the passivation layer other than the opening, and t 2 is a thickness of a region of the passivation layer between the first and second pads in the opening.

14 . The semiconductor package of claim 13 , further comprising:

an electronic component disposed on the passivation layer and having first and second external electrodes connected to the first and second pads, respectively.

15 . The semiconductor package of claim 13 , further comprising:

a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole, and

wherein the encapsulant fills at least a portion of the through-hole.

16 . The semiconductor package of claim 15 ,

wherein the frame includes a plurality of wiring layers, and

wherein the plurality of wiring layers are electrically connected to the connection pad through the redistribution layer.

17 . The semiconductor package of claim 13 , wherein the passivation layer includes a thermosetting resin.

18 . The semiconductor package of claim 13 , wherein the region of the passivation layer having the thickness t 1 is disposed directly on an insulating layer of the interconnect structure.