Memory controller, memory system, and memory control method
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
1. A memory system comprising:
a nonvolatile memory that includes a plurality of memory areas including a first memory area and a second memory area; and
a controller configured to write data into the nonvolatile memory in a first mode and a second mode, wherein:
in a case where a level of wear of the first memory area is lower than a first threshold,
the controller is configured to write data into the first memory area in the first mode in which the controller encodes a first size of data to generate a parity whose size is a second size and writes the first size of data and the generated parity into the first memory area; and
in a case where a level of wear of the second memory area is higher than the first threshold,
the controller is configured to write data into the second memory area in the second mode in which the controller encodes a third size of data to generate a parity whose size is the second size and writes the third size of data and the generated parity into the second memory area, wherein
the third size is smaller than the first size, and
an error correction capability for the data written in the second mode is higher than an error correction capability for the data written in the first mode.
2. The memory system according to claim 1 , wherein
each of the plurality of memory areas comprises a memory chip.
3. The memory system according to claim 1 , wherein
each of the plurality of memory areas comprises a block.
4. The memory system according to claim 1 , wherein
each of the plurality of memory areas comprises a page.
5. The memory system according to claim 1 , wherein
each of the plurality of memory areas comprises a memory cell group.
6. The memory system according to claim 1 , wherein
each of the plurality of memory areas comprises a unit of writing of data.
7. The memory system according to claim 6 , wherein
the controller is further configured to perform an address conversion to convert a logical address of data designated by a host into a physical address of the nonvolatile memory in which the data is stored, and
the first size is a minimum unit for the address conversion, and a sum of a plurality third sizes is the minimum unit for the address conversion.
8. The memory system according to claim 7 , wherein
the number of first size of data written in the unit of writing of data is an integer, and
the number of third size of data written in the unit of writing of data is an integer.
9. The memory system according to claim 8 , wherein
a total size of data written in the unit of writing of data in the second mode is smaller than a total size of data written in the unit of writing of data in the first mode.
10. The memory system according to claim 6 , wherein
a total size of data written in the unit of writing of data in the second mode is smaller than a total size of data written in the unit of writing of data in the first mode.
11. The memory system according to claim 1 , wherein
the level of wear of the first memory area comprises the number of write-and-erase cycles performed on the first memory area, and
the level of wear of the second memory area comprises the number of write-and-erase cycles performed on the second memory area.
12. The memory system according to claim 1 , wherein
the level of wear of the first memory area comprises a bit error ratio of data read from the first memory area, and
the level of wear of the second memory area comprises a bit error ratio of data read from the second memory area.
13. The memory system according to claim 1 , wherein
the controller is further configured to write data in the second mode in a case where a total size of parities to be stored in the second memory area is less than a second threshold.
14. The memory system according to claim 13 , wherein
the second threshold is determined so that a write performance of the memory system satisfies a predetermined performance.
15. The memory system according to claim 14 , wherein
the second threshold is further determined so that a write amplification of the memory system satisfies a third threshold.
16. A method of writing data into a nonvolatile memory that includes a plurality of memory areas including a first memory area and a second memory area, said method comprising:
in a case where a level of wear of the first memory area is lower than a first threshold,
writing data into the first memory area in the first mode in which a first size of data is encoded to generate a parity whose size is a second size and the first size of data and the generated parity are written into the first memory area; and
in a case where a level of wear of the second memory area is higher than the first threshold,
writing data into the second memory area in the second mode in which a third size of data is encoded to generate a parity whose size is the second size and the third size of data and the generated parity are written into the second memory area, wherein
the third size is smaller than the first size, and
an error correction capability for the data written in the second mode is higher than an error correction capability for the data written in the first mode.
17. The method according to claim 16 , wherein
each of the plurality of memory areas comprises a unit of writing of data.
18. The method according to claim 17 , wherein
a total size of data written in the unit of writing of data in the second mode is smaller than a total size of data written in the unit of writing of data in the first mode.
19. The method according to claim 16 , wherein
the level of wear of the first memory area comprises the number of write-and-erase cycles performed on the first memory area, and
the level of wear of the second memory area comprises the number of write-and-erase cycles performed on the second memory area.
20. The method according to claim 16 , wherein
the level of wear of the first memory area comprises a bit error ratio of data read from the first memory area, and
the level of wear of the second memory area comprises a bit error ratio of data read from the second memory area.