Multi-threshold voltage gate-all-around transistors
A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.
1. A method for forming a semiconductor device structure, the method comprising at least:
etching a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack;
crystallizing at least a portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack;
forming a dipole layer on the etched first dielectric layer and the crystallized portion of the second dielectric layer; and
diffusing the dipole layer into the etched first dielectric layer, wherein the crystallized portion prevents the dipole layer from diffusing into the second dielectric layer.
2. The method of claim 1 , further comprising:
removing at least any remaining residue from the dipole layer after diffusing the dipole layer into the etched first dielectric layer.
3. The method of claim 2 , further comprising:
forming an additional dielectric layer on and in contact with at least the etched first dielectric layer.
4. The method of claim 1 , wherein prior to removing the portion of the first dielectric layer the method further comprises:
forming a patterning layer over the at least first nanosheet stack and the at least second nanosheet stack; and
forming a masking layer over the patterning layer formed over the at least second nanosheet stack.
5. The method of claim 4 , wherein removing the portion of the first dielectric layer comprises:
etching away the patterning layer formed over the at least first nanosheet stack, wherein the etching further removes the portion of the first dielectric layer.
6. The method of claim 4 , further comprising:
removing the masking layer and the patterning layer formed over the at least second nanosheet stack prior to forming the dipole layer.
7. The method of claim 1 , wherein diffusing the dipole layer induces a threshold voltage shift at the at least first nanosheet stack such that a first device formed from the at least first nanosheet stack comprises a different threshold voltage than a second device formed from the at least second nanosheet stack.