Gate stack quality for gate-all-around field-effect transistors
View Patent ↗A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.
1. A semiconductor device, comprising:
a first gate-all-around field-effect transistor (GAA FET) device including a first vertical gate stack having a plurality of first channels, first interfacial layers formed around the first channels, and a number of first dielectric material layers including a high-k dielectric formed around the first interfacial layers, the first GAA FET including a first threshold voltage;
a second GAA FET device including a second vertical gate stack having a plurality of second channels, second interfacial layers formed around and in contact with the second channels, second gate dielectric material layers formed around and in contact with the second interfacial layers including a same number of dielectric material layers as the first dielectric material layers, one of which being a high-k dielectric layer, and a gate conductor on and in contact with the second gate dielectric material layers, the second GAA FET including a second threshold voltage;
wherein:
the first and second channels have a thickness between about 4 nm and about 8 nm;
the first and second interfacial layers have a thickness between about 0.5 nm and about 1.5 nm;
the first dielectric material layers have a combined thickness between about 1 nm and about 3 nm;
the second vertical gate stack having diffused atoms of a metal from an anneal process; and
the first threshold voltage is different than the second threshold voltage.
2. The device of claim 1 , wherein the first dielectric material layers have a thickness between about 0.5 nm and about 1 nm.
3. The device of claim 1 , wherein the first dielectric material layers are formed directly around the first interfacial layers.
4. The device of claim 1 , wherein the first vertical gate stack further includes a work function metal formed around the first dielectric material layers.