IP Library › Granted Patent US 10,224,343

Granted Patent B2

US 10,224,343 · App. 15/869,599 · Granted Mar 5, 2019

Semiconductor device and fabricating method thereof

Inventors: Bo Soon Kim (Hwaseong-si, KR); Hyun Ji Kim (Hwaseong-si, KR); Jeong Yun Lee (Yongin-si, KR); Gi Gwan Park (Hwaseong-si, KR); Sang Duk Park (Hwaseong-si, KR); Young Mook Oh (Hwaseong-si, KR); Yong Seok Lee (Hwaseong-si, KR)

Assignee: SAMSUNG ELECTRONICS CO., LTD.

H01L27/1203 H01L21/84 H01L21/845 H01L27/1211 H01L29/0673 H01L29/42392 H01L29/66439 H01L21/823456 H01L21/823462 H01L21/823468 H01L29/0653 H01L29/4908 H01L29/4966 H01L29/4991 H01L29/517 H01L29/7853

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Quick Facts

Patent No.: US 10,224,343
App. No.: 15/869,599
Granted: Mar 5, 2019
Kind: B2

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Abstract

There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.

Claims (55)

1. A semiconductor device comprising:

a substrate including a first region and a second region;

a first wire pattern provided on the first region of the substrate and spaced apart from the substrate;

a second wire pattern provided on the second region of the substrate and spaced apart from the substrate and the first wire pattern;

a first gate electrode intersecting with the first wire pattern, and overlapping the first wire pattern by a first width;

a second gate electrode intersecting the second wire pattern and overlapping the second wire pattern by a second width that is different from the first width; and

a first gate spacer disposed at opposite ends of the first wire pattern, a second gate spacer disposed at opposite ends of the second wire pattern, a first epitaxial pattern disposed at opposite sides of the first wire pattern, and a second epitaxial pattern disposed at opposite sides of the second wire pattern,

wherein the first gate electrode is disposed between the first gate spacers, and the second gate electrode is disposed between the second gate spacers, and

wherein a width of the first gate spacer disposed between the first epitaxial pattern and the first gate electrode between the substrate and the first wire pattern is different from a width of the second gate spacer disposed between the second epitaxial pattern and the second gate electrode between the substrate and the second wire pattern.

2. The semiconductor device according to claim 1 , wherein the first width is a width by which the first gate electrode and the first wire pattern overlap each other in a direction parallel to the substrate, and

the second width is a width by which the second gate electrode and the second wire pattern overlap each other in a direction parallel to the substrate.

3. The semiconductor device according to claim 1 , wherein the first gate spacer defines a first trench and the second gate spacer defines a second trench, and

the semiconductor device further comprises a first gate insulating film that extends along a sidewall of the first trench and a perimeter of the first wire pattern, and a second gate insulating film that extends along a sidewall of the second trench and a perimeter of the second wire pattern.

4. The semiconductor device according to claim 1 , further comprising a third wire pattern on the first wire pattern of the first region, the third wire pattern intersecting the first gate electrode, and

a fourth wire pattern on the second wire pattern of the second region, the fourth wire pattern intersecting the second gate electrode.

5. The semiconductor device according to claim 4 , wherein a width of the first gate electrode and the first wire pattern overlapping each other between the first wire pattern and the substrate is substantially identical to a width of the first gate electrode and the first wire pattern overlapping each other between the first wire pattern and the third wire pattern, and

a width of the second gate electrode and the second wire pattern overlapping each other between the second wire pattern and the substrate is substantially identical to a width of the second gate electrode overlapping the second wire pattern between the second wire pattern and the fourth wire pattern.

6. The semiconductor device according to claim 4 , wherein a width of the first gate electrode and the first wire pattern overlapping each other between the first wire pattern and the substrate is greater than a width of the first gate electrode and the first wire pattern overlapping each other between the first wire pattern and the third wire pattern, and

a width of the second gate electrode and the second wire pattern overlapping each other between the second wire pattern and the substrate is greater than a width of the second gate electrode and the second wire pattern overlapping each other between the second wire pattern and the fourth wire pattern.

7. A semiconductor device comprising:

a substrate including a first region and a second region;

a first wire pattern provided on the first region of the substrate and spaced apart from the substrate;

a second wire pattern provided on the first wire pattern and spaced apart from the first wire pattern;

a third wire pattern provided on the second region of the substrate and spaced apart from the substrate;

a fourth wire pattern provided on the third wire pattern and spaced apart from the third wire pattern;

a first gate spacer disposed at opposite ends of the first wire pattern and the second wire pattern;

a second gate spacer disposed at opposite ends of the third wire pattern and the fourth wire pattern, a distance between the second gate spacers between the third wire pattern and the fourth wire pattern being smaller than a distance between the first gate spacers between the first wire pattern and the second wire pattern;

a first gate electrode intersecting the first wire pattern and the second wire pattern between the first gate spacers;

a second gate electrode intersecting the third wire pattern and the fourth wire pattern between the second gate spacers; and

a first epitaxial pattern disposed at opposite sides of the first gate electrode and a second epitaxial pattern disposed at opposite sides of the second gate electrode,

wherein a width of the first gate spacer disposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the second wire pattern is smaller than a width of the second gate spacer disposed between the second epitaxial pattern and the second gate electrode between the third wire pattern and the fourth wire pattern.

8. The semiconductor device according to claim 7 , wherein a width of the first gate spacer disposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is smaller than a width of the second gate spacer disposed between the second epitaxial pattern and the second gate electrode between the third wire pattern and the substrate.

9. The semiconductor device according to claim 7 , wherein a width of the first gate electrode between the first wire pattern and the second wire pattern is greater than a width of the second gate electrode between the third wire pattern and the fourth wire pattern.

10. The semiconductor device according to claim 7 , wherein a width of the first gate electrode between the first wire pattern and the second wire pattern is substantially identical to a width of the first gate electrode between the first wire pattern and the substrate, and

a width of the second gate electrode between the third wire pattern and the fourth wire pattern is substantially identical to a width of the second gate electrode between the third wire pattern and the substrate.

11. The semiconductor device according to claim 7 , wherein a width of the first gate electrode between the first wire pattern and the second wire pattern is smaller than a width of the first gate electrode between the first wire pattern and the substrate, and

a width of the second gate electrode between the third wire pattern and the fourth wire pattern is smaller than a width of the second gate electrode between the third wire pattern and the substrate.

12. The semiconductor device according to claim 7 , wherein a height of the first gate electrode between the first wire pattern and the substrate is substantially identical to a height of the first gate electrode between the first wire pattern and the second wire pattern, and

a height of the second gate electrode between the third wire pattern and the substrate is substantially identical to a height of the second gate electrode between the third wire pattern and the fourth wire pattern.

13. The semiconductor device according to claim 7 , wherein a height of the first gate electrode between the first wire pattern and the substrate is greater than a height of the first gate electrode between the first wire pattern and the second wire pattern, and

a height of the second gate electrode between the third wire pattern and the substrate is greater than a height of the second gate electrode between the third wire pattern and the fourth wire pattern.

14. The semiconductor device according to claim 13 , wherein the first gate electrode includes a first electrode layer laminated on the first wire pattern and a second electrode layer laminated on the first electrode layer in a sequential order between the first wire pattern and the substrate.

15. The semiconductor device according to claim 13 , wherein the first gate electrode includes an air gap between the first wire pattern and the second wire pattern, but not between the first wire pattern and the substrate.

16. A semiconductor device comprising:

a substrate including a first region and a second region;

a first wire pattern provided on the first region of the substrate and spaced apart from the substrate;

a second wire pattern provided on the second region of the substrate and spaced apart from the substrate;

a first gate spacer disposed at opposite ends of the first wire pattern;

a second gate spacer disposed at opposite ends of the second wire pattern;

a first gate electrode that intersects the first wire pattern between the first gate spacers;

a second gate electrode that intersects the second wire pattern between the second gate spacers;

a first epitaxial pattern disposed at opposite sides of the first gate electrode and connected to the first wire pattern; and

a second epitaxial pattern disposed at opposite sides of the second gate electrode and connected to the second wire pattern,

wherein a width of the first gate spacer disposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is different from a width of the second gate spacer disposed between the second epitaxial pattern and the second gate electrode between the second wire pattern and the substrate, and

wherein a width of the first gate electrode between the first wire pattern and the substrate is different from a width of the second gate electrode between the second wire pattern and the substrate.

Priority Claims (2)

KR 10-2016-0003178 · Jan 11, 2016 · national

KR 10-2016-0018929 · Feb 18, 2016 · national

Continuity (2)

Continuation 15403307 · Jan 11, 2017

Related Publication 20180158836A1 · Jun 7, 2018

Cited By (2)

US 12,230,630 US 12,324,207